STM32 LLD for UART with bus idle detection

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michael_s
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STM32 LLD for UART with bus idle detection

Postby michael_s » Wed Oct 04, 2017 4:38 pm

Hello Giovanni,

I would like to upvote this feature also as we need free bus detection for our RS-485 implementation.

In addition to checking USART_SR_IDLE, it would be necessary to check the BUSY flag (bit 16) in USART_ISR register also, since USART_SR_IDLE is only set by hardware once an idle condition is present and is not cleared in case the bus becomes busy in the meantime. So, I would propose:

Code: Select all

/* Timeout interrupt source is only checked if enabled in CR1 and if BUSY flag is not set.*/
if ((sr & USART_ISR_IDLE) && (cr1 & USART_CR1_IDLEIE) && (sr & 0x10000U) {
  _uart_timeout_isr_code(uartp);
}


BUSY flag is hardcoded (0x10000U) since CMSIS header does not provide it.
What do you think?

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Re: STM32 LLD for UART with bus idle detection

Postby Korken » Wed Oct 04, 2017 6:29 pm

I also would very much like this feature.

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Re: STM32 LLD for UART with bus idle detection

Postby neums » Wed Oct 11, 2017 6:51 am

Hi,
is this item on track? I whould appreciate this feature. :-)

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Re: STM32 LLD for UART with bus idle detection

Postby Giovanni » Sun Jan 06, 2019 5:07 pm

Necro thread...

The code in the idle detection is different now, is such a change still required?

Giovanni

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Re: STM32 LLD for UART with bus idle detection

Postby michael_s » Mon Jan 07, 2019 1:22 pm

Giovanni wrote:The code in the idle detection is different now, is such a change still required?
Giovanni


Yes, I think also checking the BUSY-Bit in USART_ISR register is beneficial over just checking the IDLE-Bit in case the idle timeout shall be used to detect a "bus free" condition. By checking the BUSY-Bit, we can avoid to detect a non-idle line falsly as idle if a reception has just started and the first word is currently received.

However, as I understand, not all STM32 variants have the BUSY-Bit implemented.

Quote STM32F769 Reference Manual (page 1303):
BUSY: Busy flag
This bit is set and reset by hardware. It is active when a communication is ongoing on the
RX line (successful start bit detected). It is reset at the end of the reception (successful or
not).
0: USART is idle (no reception)
1: Reception on going


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