M4 FP register stacking/unstacking during context switch

[faisal]

I was looking thru the ChibiOS and ARM documentation trying to figure out the interrupt latency, and context switch time - and I ran across this:
http://infocenter.arm.com/help/index.js ... index.html

When dealing with systems where the FPU is used by multiple tasks, the context switching code can be designed in either of the following ways:

• The context of the FPU is always saved and restored.
• The context of the FPU is saved and restored only if the associated EXC_RETURN[4] value is 0. This means the value of CONTROL.FPCA was 1 when the task was running, before entering the context switching code.

Looking at _port_switch in ChibiOS/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.S, it seems that the floating point registers s16-s31 are always pushed/pop'd from the stack. What happens to s0-s15? What is the strategy used in ChibiOS when floating point is enabled? Also, if the FPU context is always saved and restored, doesn't that add to the context switch time if most of the threads are not using floating point (which is typically the case)? If so, any plans to make improvements in this regard? Not conditionally saving FPU context could also be beneficial in the context switching routine as that would likely necessitate the use of one or more branch instructions - so I could see why that would be preferred for some. Perhaps having a #define to choose behavior would be the best route.

[Giovanni]

ChibiOS does use the lazy stacking strategy for FP registers for interrupts except when a context switch is necessary, in that case registers stacking is enforced for obvious reasons.

During context switch not all registers are saved, just those that are assumed to be function-preserved by the compiler, it is represented by the structure port_intctx.

About improvements, feel free to propose patches for evaluation.

Giovanni

[faisal]

Thanks for the reply. If I end up making any changes, I'll be sure to submit them for wider review. Here's a couple of good discussions I've found on the topic for those interested:

Cortex-M4(F) Lazy Stacking and Context Switching
Application Note 298
http://infocenter.arm.com/help/index.js ... index.html

Cortex-M4F lazy FPU stacking
https://stackoverflow.com/questions/386 ... u-stacking
The post author Andrea Biondo, claims that the App Note (AN298) from ARM has an error and shows some proof. Also publishes his own mechanism with dealing with FP reg stacking.