I'm working on stop mode for stm32f103.
I found this thread and it was quit helpfull: viewtopic.php?t=3381#p28349
Thanks to chrismerck for sharing.
Instead of all the NOPs I found an interesting document from ARM:
http://infocenter.arm.com/help/index.js ... HFHJB.html
A DSB should be used after programming control registers, such as the System Control Register (SCR), when the side-effect is needed immediately. For example, a DSB is needed between the write to the SCS and the next operation if:the SLEEPDEEP setting in the SCR is changed, followed by either:
enter sleep with WFI/WFE
an exception exit, with Sleep-on-exit enabled.
In my example I configured a pin as external interrupt with the new pal event system. This works currently in tick-less mode.
Probably this is helpful for others, or maybe someone has a finding
Code: Select all
void stopMode() {
palEnableLineEvent(WAKEUP_LINE, PAL_EVENT_MODE_FALLING_EDGE); /* NC */
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
/* debugging */
// DBGMCU->CR |= DBGMCU_CR_DBG_STOP | DBGMCU_CR_DBG_SLEEP | DBGMCU_CR_DBG_STANDBY;
/* clear PDDS and LPDS bits */
PWR->CR &= ~(PWR_CR_PDDS | PWR_CR_LPDS);
/* set LPDS and clear */
PWR->CR |= PWR_CR_LPDS;
/* enable wakeup pin */
PWR->CSR |= PWR_CSR_EWUP;
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
__DSB();
__WFI();
chSysLock();
palDisableLineEventI(WAKEUP_LINE);
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
PWR->CR |= PWR_CR_CWUF;
PWR->CR |= PWR_CR_CSBF;
stm32_clock_init();
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
chSysUnlock();
}