See patches below:
Code: Select all
Left base folder: /chibios-svn2-stable_18.2.x/os
Right base folder: /ChibiOS_18.2.0/os
*** hal/ports/STM32/STM32F7xx/stm32_rcc.h 2018-03-17 21:17:25.000000000
--- hal/ports/STM32/STM32F7xx/stm32_rcc.h 2018-03-16 15:23:21.000000000
***************
*** 744,755 ****
--- 744,785 ----
* @api
*/
#define rccResetQUADSPI1() rccResetAHB3(RCC_AHB3RSTR_QSPIRST)
/** @} */
/**
+ * @name RNG peripheral specific RCC operations
+ * @{
+ */
+ /**
+ * @brief Enables the RNG peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+ #define rccEnableRNG(lp) rccEnableAHB2(RCC_AHB2ENR_RNGEN, lp)
+
+ /**
+ * @brief Disables the RNG peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+ #define rccDisableRNG(lp) rccDisableAHB2(RCC_AHB2ENR_RNGEN)
+
+ /**
+ * @brief Resets the RNG peripheral.
+ *
+ * @api
+ */
+ #define rccResetRNG() rccResetAHB2(RCC_AHB2RSTR_RNGRST)
+ /** @} */
+
+ /**
* @name SDMMC peripheral specific RCC operations
* @{
*/
/**
* @brief Enables the SDMMC1 peripheral clock.
*
Code: Select all
Left base folder: /chibios-svn2-stable_18.2.x/os
Right base folder: /ChibiOS_18.2.0/os
*** hal/ports/STM32/STM32F7xx/stm32_registry.h 2018-03-17 21:17:24.000000000
--- hal/ports/STM32/STM32F7xx/stm32_registry.h 2018-03-17 21:57:35.000000000
***************
*** 201,212 ****
--- 201,217 ----
#define STM32_HAS_QUADSPI1 TRUE
#define STM32_QUADSPI1_HANDLER Vector1B0
#define STM32_QUADSPI1_NUMBER 92
#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
#define STM32_QUADSPI1_DMA_CHN 0x30000000
+ /* RNG attributes */
+ #define STM32_HAS_RNG TRUE
+ #define STM32_RNG_HANDLER Vector180
+ #define STM32_RNG_IRQ_NUMBER 80
+
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
#define STM32_RTC_NUM_ALARMS 2
#define STM32_RTC_HAS_INTERRUPTS FALSE
***************
*** 688,699 ****
--- 693,709 ----
#define STM32_HAS_QUADSPI1 TRUE
#define STM32_QUADSPI1_HANDLER Vector1B0
#define STM32_QUADSPI1_NUMBER 92
#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
#define STM32_QUADSPI1_DMA_CHN 0x30000000
+ /* RNG attributes */
+ #define STM32_HAS_RNG TRUE
+ #define STM32_RNG_HANDLER Vector180
+ #define STM32_RNG_IRQ_NUMBER 80
+
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
#define STM32_RTC_NUM_ALARMS 2
#define STM32_RTC_HAS_INTERRUPTS FALSE
***************
*** 1185,1196 ****
--- 1195,1211 ----
#define STM32_QUADSPI1_HANDLER Vector1B0
#define STM32_QUADSPI1_NUMBER 92
#define STM32_QUADSPI1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
STM32_DMA_STREAM_ID_MSK(2, 7))
#define STM32_QUADSPI1_DMA_CHN 0x30000B00
+ /* RNG attributes */
+ #define STM32_HAS_RNG TRUE
+ #define STM32_RNG_HANDLER Vector180
+ #define STM32_RNG_IRQ_NUMBER 80
+
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
#define STM32_RTC_NUM_ALARMS 2
#define STM32_RTC_HAS_INTERRUPTS FALSE
Code: Select all
Left base folder: /chibios-svn2-stable_18.2.x/os
Right base folder: /ChibiOS_18.2.0/os
*** hal/ports/STM32/STM32L4xx/stm32_rcc.h 2018-03-17 21:17:26.000000000
--- hal/ports/STM32/STM32L4xx/stm32_rcc.h 2018-03-16 15:23:22.000000000
***************
*** 576,587 ****
--- 576,618 ----
* @api
*/
#define rccResetQUADSPI1() rccResetAHB3(RCC_AHB3RSTR_QSPIRST)
/** @} */
/**
+ * @name RNG peripheral specific RCC operations
+ * @{
+ */
+ /**
+ * @brief Enables the RNG peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+ #define rccEnableRNG(lp) rccEnableAHB2(RCC_AHB2ENR_RNGEN, lp)
+
+ /**
+ * @brief Disables the RNG peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+ #define rccDisableRNG(lp) rccDisableAHB2(RCC_AHB2ENR_RNGEN)
+
+ /**
+ * @brief Resets the RNG peripheral.
+ *
+ * @api
+ */
+ #define rccResetRNG() rccResetAHB2(RCC_AHB2RSTR_RNGRST)
+ /** @} */
+
+
+ /**
* @name SDMMC peripheral specific RCC operations
* @{
*/
/**
* @brief Enables the SDMMC1 peripheral clock.
*
Code: Select all
Left base folder: /chibios-svn2-stable_18.2.x/os
Right base folder: /ChibiOS_18.2.0/os
*** hal/ports/STM32/STM32L4xx/stm32_registry.h 2018-03-17 21:17:26.000000000
--- hal/ports/STM32/STM32L4xx/stm32_registry.h 2018-03-17 22:01:13.000000000
***************
*** 215,226 ****
--- 215,231 ----
#define STM32_QUADSPI1_HANDLER Vector15C
#define STM32_QUADSPI1_NUMBER 71
#define STM32_QUADSPI1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
STM32_DMA_STREAM_ID_MSK(2, 7))
#define STM32_QUADSPI1_DMA_CHN 0x03050000
+ /* RNG attributes */
+ #define STM32_HAS_RNG TRUE
+ #define STM32_RNG_HANDLER Vector180
+ #define STM32_RNG_IRQ_NUMBER 80
+
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
#define STM32_RTC_NUM_ALARMS 2
#define STM32_RTC_HAS_INTERRUPTS FALSE
***************
*** 561,572 ****
--- 566,582 ----
#define STM32_QUADSPI1_HANDLER Vector15C
#define STM32_QUADSPI1_NUMBER 71
#define STM32_QUADSPI1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
STM32_DMA_STREAM_ID_MSK(2, 7))
#define STM32_QUADSPI1_DMA_CHN 0x03050000
+ /* RNG attributes */
+ #define STM32_HAS_RNG TRUE
+ #define STM32_RNG_HANDLER Vector180
+ #define STM32_RNG_IRQ_NUMBER 80
+
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
#define STM32_RTC_NUM_ALARMS 2
#define STM32_RTC_HAS_INTERRUPTS FALSE
***************
*** 922,933 ****
--- 932,948 ----
#define STM32_QUADSPI1_HANDLER Vector15C
#define STM32_QUADSPI1_NUMBER 71
#define STM32_QUADSPI1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
STM32_DMA_STREAM_ID_MSK(2, 7))
#define STM32_QUADSPI1_DMA_CHN 0x03050000
+ /* RNG attributes */
+ #define STM32_HAS_RNG TRUE
+ #define STM32_RNG_HANDLER Vector180
+ #define STM32_RNG_IRQ_NUMBER 80
+
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
#define STM32_RTC_NUM_ALARMS 2
#define STM32_RTC_HAS_INTERRUPTS FALSE
***************
*** 1346,1357 ****
--- 1361,1377 ----
#define STM32_QUADSPI1_HANDLER Vector15C
#define STM32_QUADSPI1_NUMBER 71
#define STM32_QUADSPI1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
STM32_DMA_STREAM_ID_MSK(2, 7))
#define STM32_QUADSPI1_DMA_CHN 0x03050000
+ /* RNG attributes */
+ #define STM32_HAS_RNG TRUE
+ #define STM32_RNG_HANDLER Vector180
+ #define STM32_RNG_IRQ_NUMBER 80
+
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
#define STM32_RTC_NUM_ALARMS 2
#define STM32_RTC_HAS_INTERRUPTS FALSE