STM32H7 ADCv4 dual mode DMA issue
Posted: Wed Jul 29, 2020 11:27 am
I did discover another problem with ADCv4 in dual mode, which is not really in ChibiOS but appears to be in the hardware.
The readings from the slave ADC are delayed by one sample. This is because the DMA transfer seems to be triggered by the master EOC, just before the slave has put the data into the CDR.
When I select the same sample time for master and slave the DMA reads the previous slave sample. When the slave sample time is shorter than the master sample time it works correctly. When the sample time of the slave is larger than the master sample time the DMA transfer is triggered at the master EOC, so way before the slave is finished.
Figure 202 of RM0433 (page 996) very clearly shows that the DMA request should only be triggered after both master and slave EOC, but appears to be always triggered after the master EOC.
This issue is already on the ST community forum: https://community.st.com/s/question/0D7 ... =1&s1ext=0
There is no answer from ST yet, but it appears the HAL should be changed to used 2 DMA channels instead of one, but I don't know if that can be done without API changes. Hopefully there is still a way to get it working.
The readings from the slave ADC are delayed by one sample. This is because the DMA transfer seems to be triggered by the master EOC, just before the slave has put the data into the CDR.
When I select the same sample time for master and slave the DMA reads the previous slave sample. When the slave sample time is shorter than the master sample time it works correctly. When the sample time of the slave is larger than the master sample time the DMA transfer is triggered at the master EOC, so way before the slave is finished.
Figure 202 of RM0433 (page 996) very clearly shows that the DMA request should only be triggered after both master and slave EOC, but appears to be always triggered after the master EOC.
This issue is already on the ST community forum: https://community.st.com/s/question/0D7 ... =1&s1ext=0
There is no answer from ST yet, but it appears the HAL should be changed to used 2 DMA channels instead of one, but I don't know if that can be done without API changes. Hopefully there is still a way to get it working.