I did discover another problem with ADCv4 in dual mode, which is not really in ChibiOS but appears to be in the hardware.
The readings from the slave ADC are delayed by one sample. This is because the DMA transfer seems to be triggered by the master EOC, just before the slave has put the data into the CDR.
When I select the same sample time for master and slave the DMA reads the previous slave sample. When the slave sample time is shorter than the master sample time it works correctly. When the sample time of the slave is larger than the master sample time the DMA transfer is triggered at the master EOC, so way before the slave is finished.
Figure 202 of RM0433 (page 996) very clearly shows that the DMA request should only be triggered after both master and slave EOC, but appears to be always triggered after the master EOC.
This issue is already on the ST community forum: https://community.st.com/s/question/0D7 ... =1&s1ext=0
There is no answer from ST yet, but it appears the HAL should be changed to used 2 DMA channels instead of one, but I don't know if that can be done without API changes. Hopefully there is still a way to get it working.
STM32H7 ADCv4 dual mode DMA issue
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Re: STM32H7 ADCv4 dual mode DMA issue
It is obviously an HW problem.
Is it possible to have the (single) DMA be triggered by the slave ADC? in that moment the master sample should already be available. It would be worth trying.
Giovanni
Is it possible to have the (single) DMA be triggered by the slave ADC? in that moment the master sample should already be available. It would be worth trying.
Giovanni
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Re: STM32H7 ADCv4 dual mode DMA issue
Just a note about dual DMA "solution", it would not fit our HAL, that would mean having 2 circular buffers, one for each ADC, the API does not support that.
Giovanni
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Re: STM32H7 ADCv4 dual mode DMA issue
Giovanni wrote:Is it possible to have the (single) DMA be triggered by the slave ADC?
Good idea. I did a quick test by using
Code: Select all
dmaSetRequestSource(adcp->data.dma, STM32_DMAMUX1_ADC2);
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Re: STM32H7 ADCv4 dual mode DMA issue
I've tried the dual ADC mode a bit more, and found out that sometimes it does trigger correctly, sometimes not. In the current firmware it triggers correctly, the DMA is called when both samples are in the CDR register. Then after a couple of minutes it changes and the DMA is called when only the ADC1 result is in the CDR and the the previous sample of ADC2 is still there.
This makes it very hard to debug, first it was wrong directly after boot, now only after some minutes. Maybe in another case it can function correctly for hours and then change. I have no idea how to reliably solve this. Maybe it depends on the clock settings or so?
I didn't test the STM HAL adc driver yet, that might shed some light on the issue.
For my case I'm leaning towards implementing a version of the ADC driver without DMA, since I only have two channels per ADC that would only be one extra interrupt per cycle. (for the moment I switched to using a single ADC, but I could really use the extra speed of dual mode)
This makes it very hard to debug, first it was wrong directly after boot, now only after some minutes. Maybe in another case it can function correctly for hours and then change. I have no idea how to reliably solve this. Maybe it depends on the clock settings or so?
I didn't test the STM HAL adc driver yet, that might shed some light on the issue.
For my case I'm leaning towards implementing a version of the ADC driver without DMA, since I only have two channels per ADC that would only be one extra interrupt per cycle. (for the moment I switched to using a single ADC, but I could really use the extra speed of dual mode)
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