There are a few things in ADCv3 that can be updated I think.
1. The Error and AWDG interrupts are enabled when there is no callback.
2. AWD2 and AWD3 are not catered for in config.
--
Bob
Code: Select all
Index: hal_adc_lld.c
===================================================================
--- hal_adc_lld.c (revision 13789)
+++ hal_adc_lld.c (working copy)
@@ -847,11 +847,18 @@
dmaStreamSetMode(adcp->dmastp, dmamode);
dmaStreamEnable(adcp->dmastp);
- /* ADC setup, if it is defined a callback for the analog watch dog then it
- is enabled.*/
+ /* Clear any interrupts. If an error callback is defined then enable
+ overflow and analog watchdog interrupts. */
adcp->adcm->ISR = adcp->adcm->ISR;
- adcp->adcm->IER = ADC_IER_OVRIE | ADC_IER_AWD1IE;
- adcp->adcm->TR1 = grpp->tr1;
+ if (grpp->error_cb != NULL) {
+ adcp->adcm->IER = ADC_IER_OVRIE | ADC_IER_AWD1IE
+ | ADC_IER_AWD2IE
+ | ADC_IER_AWD3IE;
+ adcp->adcm->TR1 = grpp->tr1;
+ adcp->adcm->TR2 = grpp->tr2;
+ adcp->adcm->TR3 = grpp->tr3;
+ }
+
#if STM32_ADC_DUAL_MODE
/* Configuring the CCR register with the user-specified settings
Index: hal_adc_lld.h
===================================================================
--- hal_adc_lld.h (revision 13789)
+++ hal_adc_lld.h (working copy)
@@ -851,10 +851,14 @@
specified in continuous mode or if the buffer depth is \
greater than one.*/ \
uint32_t cfgr; \
- /* ADC CFGR2 register initialization data.*/ \
+ /* ADC CFGR2 register initialization data.*/ \
uint32_t cfgr2; \
/* ADC TR1 register initialization data.*/ \
uint32_t tr1; \
+ /* ADC TR2 register initialization data.*/ \
+ uint32_t tr2; \
+ /* ADC TR3 register initialization data.*/ \
+ uint32_t tr3; \
/* ADC CCR register initialization data. \
NOTE: Put this field to zero if not using oversampling.*/ \
uint32_t ccr; \
@@ -873,6 +877,8 @@
uint32_t cfgr; \
uint32_t cfgr2; \
uint32_t tr1; \
+ uint32_t tr2; \
+ uint32_t tr3; \
uint32_t smpr[2]; \
uint32_t sqr[4]
#endif /* STM32_ADC_DUAL_MODE == FALSE */
@@ -882,6 +888,8 @@
#define adc_lld_configuration_group_fields \
uint32_t cfgr; \
uint32_t tr1; \
+ uint32_t tr2; \
+ uint32_t tr3; \
uint32_t ccr; \
uint32_t smpr[2]; \
uint32_t sqr[4]; \
@@ -891,6 +899,8 @@
#define adc_lld_configuration_group_fields \
uint32_t cfgr; \
uint32_t tr1; \
+ uint32_t tr2; \
+ uint32_t tr3; \
uint32_t smpr[2]; \
uint32_t sqr[4]
#endif /* STM32_ADC_DUAL_MODE == FALSE */
