L4/L4+ ADC clock Topic is solved

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L4/L4+ ADC clock

Postby FXCoder » Sun Mar 29, 2020 4:23 am

Hi,
L4/L4+ allow PLLSAI1R or SYSCLK as ADC clock source supplying the "AHB" prescaler.
In ADCv3 the test of the selected ADC clock frequency for L4/L4+ is done against STM32_HCLK.
The check should be against STM32_ADCCLK.
--
Bob

Code: Select all


Index: os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h
===================================================================
--- os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h   (revision 13487)
+++ os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h   (working copy)
@@ -717,11 +717,11 @@
 #if STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
 #define STM32_ADC123_CLOCK              (STM32_ADCCLK / ADC123_PRESC_VALUE)
 #elif STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC123_CLOCK              (STM32_HCLK / 1)
+#define STM32_ADC123_CLOCK              (STM32_ADCCLK / 1)
 #elif STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
-#define STM32_ADC123_CLOCK              (STM32_HCLK / 2)
+#define STM32_ADC123_CLOCK              (STM32_ADCCLK / 2)
 #elif STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
-#define STM32_ADC123_CLOCK              (STM32_HCLK / 4)
+#define STM32_ADC123_CLOCK              (STM32_ADCCLK / 4)
 #else
 #error "invalid clock mode selected for STM32_ADC_ADC123_CLOCK_MODE"
 #endif

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Re: L4/L4+ ADC clock  Topic is solved

Postby FXCoder » Thu Apr 02, 2020 10:29 am

Fixed as bug #1079


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