My MCU is stmf405.
From time to time, my program gets stuck inside the otg_core_reset() in the following endless loop:
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/* Core reset and delay of at least 3 PHY cycles.*/
otgp->GRSTCTL = GRSTCTL_CSRST;
while ((otgp->GRSTCTL & GRSTCTL_CSRST) != 0)
;
According to the MCU RM:
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The application can flush the entire RxFIFO using this bit, but must first ensure that the core
is not in the middle of a transaction.
The application must only write to this bit after checking that the core is neither reading from
the RxFIFO nor writing to the RxFIFO.
The way to check this condition is to test the AHBIDL bit. The otg_core_reset() does this, but by some unknown reasons AFTER writing the GRSTCTL_CSRST bit, not before
Regards,
Vladimir
PS: the "official" ST HAL library tests the AHBIDL before writing the GRSTCTL_CSRST.