Make the L476 ADC demo work Topic is solved

[rreignier]

Hi,

I have been trying to get the STM32L4xx ADC demo (testhal/STM32/STM32L4xx/ADC) work on Nucleo64 L476RG board.

I use the branch stable_18.2.x from the SVN.

I have done the following changes to print the adc results on the serial port:

Code: Select all

diff --git a/testhal/STM32/STM32L4xx/ADC/main.c b/testhal/STM32/STM32L4xx/ADC/main.c
index ee950f2..ca2a3cd 100644
--- a/testhal/STM32/STM32L4xx/ADC/main.c
+++ b/testhal/STM32/STM32L4xx/ADC/main.c
@@ -16,6 +16,7 @@
 
 #include "ch.h"
 #include "hal.h"
+#include "chprintf.h"
 
 #define ADC_GRP1_NUM_CHANNELS   2
 #define ADC_GRP1_BUF_DEPTH      8
@@ -50,7 +51,7 @@ static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) {
 /*
  * ADC conversion group.
  * Mode:        Linear buffer, 8 samples of 2 channels, SW triggered.
- * Channels:    IN1, IN11.
+ * Channels:    IN1, IN2.
  * Notes:       IN1 = PC0, IN2 = PC1
  */
 static const ADCConversionGroup adcgrpcfg1 = {
@@ -133,11 +134,24 @@ int main(void) {
   chSysInit();
 
   /*
+   * Activates the serial driver 2 using the driver default configuration.
+   */
+  sdStart(&SD2, NULL);
+
+  /*
    * Creates the blinker thread.
    */
   chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);

   /*
+   * Setting up analog inputs used by the demo.
+   */
+  palSetGroupMode(GPIOA, PAL_PORT_BIT(0) | PAL_PORT_BIT(1),
+                  0, PAL_MODE_INPUT_ANALOG);
+  palSetGroupMode(GPIOC, PAL_PORT_BIT(0) | PAL_PORT_BIT(1),
+                  0, PAL_MODE_INPUT_ANALOG);
+
+  /*
    * Activates the ADC1 driver and the temperature sensor.
    */
   adcStart(&ADCD1, NULL);
@@ -150,6 +164,14 @@ int main(void) {
   adcConvert(&ADCD1, &adcgrpcfg1, samples1, ADC_GRP1_BUF_DEPTH);
   chThdSleepMilliseconds(1000);

+  chprintf((BaseSequentialStream*)&SD2, "Samples 1\r\n");
+  int i;
+  for(i = 0; i < (ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH); ++i)
+  {
+     chprintf((BaseSequentialStream*)&SD2, "Value %d: %d\r\n", i, samples1[i]);
+  }
+  chprintf((BaseSequentialStream*)&SD2, "\n");
+
   /*
    * Starts an ADC continuous conversion.
    */
@@ -159,9 +181,20 @@ int main(void) {
    * Normal main() thread activity, in this demo it does nothing.
    */
   while (true) {
+    /*
     if (palReadPad(GPIOC, GPIOC_BUTTON)) {
       adcStopConversion(&ADCD1);
     }
+    */
+
+    chprintf((BaseSequentialStream*)&SD2, "Samples 2\r\n");
+    int i;
+    for(i = 0; i < (ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH); ++i)
+    {
+       chprintf((BaseSequentialStream*)&SD2, "Value %d: %d\r\n", i, samples2[i]);
+    }
+    chprintf((BaseSequentialStream*)&SD2, "\n");
+
     chThdSleepMilliseconds(500);
   }
 }


Altough, I only get variation on the PA0 and PC0 pins when I short thenm to GND. Nothing on PA1 and PC1.

I had the same result on the testhal/STM32/STM32L4xx/GPT-ADC demo with the following changes:

Code: Select all

diff --git a/testhal/STM32/STM32L4xx/GPT-ADC/main.c b/testhal/STM32/STM32L4xx/GPT-ADC/main.c
index 2ff6150..627f58e 100644
--- a/testhal/STM32/STM32L4xx/GPT-ADC/main.c
+++ b/testhal/STM32/STM32L4xx/GPT-ADC/main.c
@@ -16,6 +16,7 @@

 #include "ch.h"
 #include "hal.h"
+#include "chprintf.h"

 /*===========================================================================*/
 /* GPT driver related.                                                       */
@@ -81,11 +82,11 @@ static const ADCConversionGroup adcgrpcfg1 = {
   ADC_TR(0, 4095),                                                 /* TR1    */
   {                                                                /* SMPR[2]*/
     ADC_SMPR1_SMP_AN0(ADC_SMPR_SMP_247P5) |
-    ADC_SMPR1_SMP_AN5(ADC_SMPR_SMP_247P5),
+    ADC_SMPR1_SMP_AN6(ADC_SMPR_SMP_247P5),
     0
   },
   {                                                                /* SQR[4] */
-    ADC_SQR1_SQ1_N(ADC_CHANNEL_IN0) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN5),
+    ADC_SQR1_SQ1_N(ADC_CHANNEL_IN0) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN6),
     0,
     0,
     0
@@ -146,7 +147,7 @@ int main(void) {
   adcSTM32EnableVREF(&ADCD1);
   adcSTM32EnableTS(&ADCD1);

-  palSetLineMode(LINE_ARD_A0, PAL_MODE_INPUT_ANALOG);
+  palSetLineMode(LINE_ARD_A1, PAL_MODE_INPUT_ANALOG);

   /*
    * Starts an ADC continuous conversion triggered with a period of
@@ -164,6 +165,13 @@ int main(void) {
    * Normal main() thread activity, in this demo it does nothing.
    */
   while (true) {
+    int i;
+    for(i = 0; i < (ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH); ++i)
+    {
+       chprintf((BaseSequentialStream*)&SD2, "Value %d: %d\r\n", i, samples1[i]);
+    }
+    chprintf((BaseSequentialStream*)&SD2, "\n");
+
     chThdSleepMilliseconds(500);
   }
 }


So, am I missing something?

Thanks

[rreignier]

I have finally found the solution, there is a bug in GPIOv3, only the first bit of the ASCR register is set, see the following patch:

Code: Select all

diff --git a/os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c b/os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c
index c2dcf7b..e1f63d3 100644
--- a/os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c
+++ b/os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c
@@ -141,6 +141,7 @@ void _pal_lld_setgroupmode(ioportid_t port,
     if (!mask)
       return;
     otyper <<= 1;
+    ascr <<= 1;
     ospeedr <<= 2;
     pupdr <<= 2;
     moder <<= 2;


But note that according to RM0351, only the STM32L475xx/476xx/486xx devices have that register.

I think this thread should be moved to the Bug Report category.

Thanks

[Giovanni]

Hi,

Thanks for finding, moving in bug reports.

Giovanni

[Giovanni]

Hi,

Fixed as bug #949.

The missing ASCR register on L43/L44/L45 devices is harmless, it should use GPIOv2 but that would create a lot of problems with board files generation so I will leave it GPIOv3.

Giovanni