STM32_PLL48CLK configuration error in hal_lld.h Topic is solved

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faisal
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STM32_PLL48CLK configuration error in hal_lld.h  Topic is solved

Postby faisal » Tue Mar 20, 2018 10:59 pm

See attachment, taken from TRM.

Index: os/hal/ports/STM32/STM32F7xx/hal_lld.h
===================================================================
--- os/hal/ports/STM32/STM32F7xx/hal_lld.h (revision 11829)
+++ os/hal/ports/STM32/STM32F7xx/hal_lld.h (working copy)
@@ -1941,7 +1941,7 @@
#if (STM32_CK48MSEL == STM32_CK48MSEL_PLL) || defined(__DOXYGEN__)
#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
#elif STM32_CK48MSEL == STM32_CK48MSEL_PLLSAI
-#define STM32_PLL48CLK (STM32_PLLSAIVCO / STM32_PLLSAIQ_VALUE)
+#define STM32_PLL48CLK (STM32_PLLSAIVCO / STM32_PLLSAIP_VALUE)
#else
#error "invalid source selected for PLL48CLK clock"
#endif
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Giovanni
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Re: STM32_PLL48CLK configuration error in hal_lld.h

Postby Giovanni » Fri Mar 23, 2018 1:51 pm

Hi,

Fixed as bug #929.

Giovanni


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