Priority order violation - Asserion fails Topic is solved

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Giovanni
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Re: Priority order violation - Asserion fails

Postby Giovanni » Sat Mar 16, 2019 4:58 pm

After thinking about this, adding a counter would not work, an ISR could be preempted by another ISR before the counter is increased and that would trigger another problem.

A possible solution could be to use PendSV, placed at lowest priority, as tail IRQ when a preemption is required but the risk is to decrease performance, I need to think about this.

The best approach so far is to document that ISRs without OS macros must be placed at higher priority than any ISR interacting with the OS.

Giovanni

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Giovanni
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Re: Priority order violation - Asserion fails

Postby Giovanni » Sun Mar 31, 2019 9:28 am

Hi,

As solution for this kind of issues I added this new article: http://www.chibios.org/dokuwiki/doku.ph ... texm_notes

Giovanni


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