STM32 rcc changes changes LPENR behavior Topic is solved

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STM32 rcc changes changes LPENR behavior  Topic is solved

Postby pl4nkton » Tue Jan 16, 2018 12:30 am

Hello Giovanni,
the change to remove lowpower config from RCC clockdisable macros e.g. leads to a non working can interface.

From RM0385
RCC APB1 peripheral clock enable in low-power mode register
(RCC_APB1LPENR)
Address offset: 0x60
Reset value: 0xFFFF CBFFh


So the default is that all hardware units get clock in sleep mode.
The old code did not touch the lpenr registers.

rccEnablexxx
if (lp) \
RCC->xxxLPENR |= (mask);

rccDisablexxx
if (lp) \
RCC->xxxLPENR &= ~(mask);

But the now the bit is cleared in the lpenr register if rccdisable is called - like in the setup of the can hardware.

#define rccDisablexxx(mask) { \
RCC->xxxENR &= ~(mask); \
RCC->xxxLPENR &= ~(mask);

best regards
nicolas

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Re: STM32 rcc changes changes LPENR behavior

Postby Giovanni » Tue Jan 16, 2018 8:31 am

Hi,

It is an intentional change, regardless of the post-reset state, what is the point in keeping clocks enabled in sleep mode and disabled in run mode?

I don't understand how it breaks the CAN interface, could you give some details?

Giovanni

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Re: STM32 rcc changes changes LPENR behavior

Postby pl4nkton » Wed Jan 17, 2018 11:20 am

what is the point in keeping clocks enabled in sleep mode and disabled in run mode?


Did you mean
what is the point in keeping clocks disabled in sleep mode and enabled in run mode?


The Problem is that the CPU puts a message to the mailbox, goes to sleep and the CAN block clock gets switched off. -> No message send or the transmission breaks while sending.
Also it is not possible to receive messages without clock.

Until the commit every driver had set LPENR config to false and so the default register settings - what is 1 to enable clock while sleep - was not modified.
But the change modifies the previous behaviour and now the lpenr bit is set to 0 once rccdisable is called.

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Re: STM32 rcc changes changes LPENR behavior

Postby Giovanni » Wed Jan 17, 2018 11:41 am

Hi,

I meant exactly that, the default value of LPENR register is "enabled" which makes no sense because ENR registers are defaulted to "disabled". I am missing something here.

Probably the best thing to do is to change rccXXXEnable() calls to true for all drivers. LPENR registers should cleared on start.

Giovanni

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Re: STM32 rcc changes changes LPENR behavior

Postby Giovanni » Wed Jan 17, 2018 11:49 am

OK, I see now.

When ENR bits are set to zero then LPENR bits are "don't care".

I think I will change this way:
- rccXXXXEnable() functions will enable or disable LPENR bits depending on the parameter.
- rccXXXXDisable() functions will not touch LPENR because it does nothing (saves code space).
- All driver will be defaulted to enable the LPENR bit by setting the parameter to "true", user can change this by resetting the LPENR bit after calling xxxStart().

Giovanni

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Re: STM32 rcc changes changes LPENR behavior

Postby pl4nkton » Wed Jan 17, 2018 2:42 pm

Fine.
Thank you.

Nicolas

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Re: STM32 rcc changes changes LPENR behavior

Postby Giovanni » Wed Jan 17, 2018 5:35 pm

Changes committed.

Giovanni


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