STM32F3xx ADC common control register initialisation bug Topic is solved

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mspieler
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STM32F3xx ADC common control register initialisation bug  Topic is solved

Postby mspieler » Thu Oct 19, 2017 8:03 pm

Hi,

We discovered that the defines STM32_ADC_ADC12_CLOCK_MODE and ADC_DMA_MDMA are never written to the ADCx_COMMON->CCR register in adc_lld_init().

The issue is on following lines in ChibiOS/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c:544

Code: Select all

#if STM32_ADC_USE_ADC1
  rccEnableADC12(FALSE);
  rccResetADC12();
  ADC1_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
  rccDisableADC12(FALSE);
#endif


We found the following workaround:

Code: Select all

#if STM32_ADC_USE_ADC1
  rccEnableADC12(FALSE);
  rccResetADC12();
  __NOP(); // wait for peripheral to reset/turn on
  ADC1_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
  rccDisableADC12(FALSE);
#endif


ChibiOS version: GitHub mirror, branch chibios/stable_17.6.x, commit 05c21e002f4b943a4b04e36c76c73e03cecd3cc6
Compiler: arm-none-eabi-gcc (GNU Tools for ARM Embedded Processors 6-2017-q2-update) 6.3.1 20170620
Platform: STM32F303CCT6
Board: https://github.com/cvra/motor-control-board
Source: https://github.com/cvra/robot-software/ ... l-firmware

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Re: STM32F3xx ADC common control register initialisation bug

Postby Giovanni » Sun May 27, 2018 9:04 am

bump

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Re: STM32F3xx ADC common control register initialisation bug

Postby Giovanni » Fri Jun 01, 2018 8:32 am

Hi,

I added a delay to the ADCv3 driver in trunk.

Fixed as bug #953.

Giovanni

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Re: STM32F3xx ADC common control register initialisation bug

Postby faisal » Sat Jul 07, 2018 1:24 am

The bug fix results in being stuck in the ADC LLD init. This is because port init is called in chsysinit, which is where the cycle counter is enabled. ADC LLD init calls osalSysPolledDelayX(10), which uses the cycle counter. Chsysinit is called after halinit.

It was likely not caught because if you run it in a debugger, the debugger enables the setting in the debug registers. But if you run standalone, it doesn't work.

HAL needs a scrub and some documentation that clarifies you can't use polleddelayx API in the lld init function.

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Re: STM32F3xx ADC common control register initialisation bug

Postby Giovanni » Sat Jul 07, 2018 9:27 am

Hi,

In trunk and 18.2.x I fixed this in the RCC macros by adding a read-back of the modified registers (all platforms), this should ensure that the RCC write operation has been completed on the bus before proceeding. On 17.6.x I added the __NOP() as suggested.

Giovanni


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