F04/07/09 clock definitions

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F04/07/09 clock definitions

Postby steved » Fri Sep 22, 2017 2:12 pm

The 32F04/07/09 don't have a divide by two on the output of the HSI clock into the PLL. However it's currently allowed, and used in the demo:

Code: Select all

#if 0
// original demo code
#define STM32_PLLSRC                        STM32_PLLSRC_HSI_DIV2
#define STM32_PREDIV_VALUE                  1
// F091 doesn't have divide by 2
#define STM32_PLLSRC                        STM32_PLLSRC_HSI
#define STM32_PREDIV_VALUE                  2

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