F04/07/09 clock definitions Topic is solved

[steved]

The 32F04/07/09 don't have a divide by two on the output of the HSI clock into the PLL. However it's currently allowed, and used in the demo:

Code: Select all

#if 0
// original demo code
#define STM32_PLLSRC                        STM32_PLLSRC_HSI_DIV2
#define STM32_PREDIV_VALUE                  1
#else
// F091 doesn't have divide by 2
#define STM32_PLLSRC                        STM32_PLLSRC_HSI
#define STM32_PREDIV_VALUE                  2
#endif


[Giovanni]

bump

[Giovanni]

Hi,

About this, the RM0091 manual states"

"00: HSI/2 selected as PLL input clock (PREDIV forced to divide by 2 on STM32F04x, STM32F07x and STM32F09x devices)"

Apparently the setting does exist and forces PREDIV to emulate previous devices. Is a change required with this behavior?

Giovanni

[steved]

Hi,

About this, the RM0091 manual states"

"00: HSI/2 selected as PLL input clock (PREDIV forced to divide by 2 on STM32F04x, STM32F07x and STM32F09x devices)"

Apparently the setting does exist and forces PREDIV to emulate previous devices. Is a change required with this behavior?

Giovanni

Have to dig a bit more to be absolutely confident, but does look as if that bit of 'small print' makes everything work out.
I've got an F091 board to bring up over the next few weeks; will try and have a play.