Interesting, that is on the F7 which has a FIFO but flushing the data register after stopping the master clock and DMAs could be a solution. Another option would be to reset the SPI peripheral on i2sStart().
Report here problems in any of ChibiOS components. This forum is NOT for support.
I've managed to recover from this problem. Before starting DMA, I explicitly fetch a few half-words from the I2S data register, and find where the sample start sequence begins. Unfortunately, this solution is not universal: is works for my particular codec chip
Who is online
Users browsing this forum: No registered users and 2 guests