Cortex-M7 platform FatFS Cache coherency Topic is solved

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Cortex-M7 platform FatFS Cache coherency  Topic is solved

Postby cpu20 » Tue May 23, 2017 8:46 pm

- So after running into problems with the M7 cache coherency and my SPI driver (thanks to Giovanni for helping me with that!) I also found that the same problems occur when using the FatFS libary on the M7-platform.
- Currently I am using ChibiOS_16.1.8
- Compiled with gcc-arm-none-eabi-5_4-2016q2
- The board I have tested this on is the STM32F746G-DISCO in Eclipse.
- The problem occurs when trying to read from or write to the disk with FatFS and the FIL-variable passed to the read/write function is allocated from the heap. When using chHeapAlloc to allocate the FIL-variable nothing is returned when reading from and nothing is written when writing to the disk. This also occurs when creating a thread with 'chThdCreateFromHeap' and the FIL-variable is created in the thread, because then it is also allocated from the heap.
- The reason for the failure is that the FIL-variable isn't flushed to cache when writing and isn't being invalidated when reading from the disk.
- In the attachment I have included a fix for this in the fatfs_diskio.c file. The only thing I am not sure of, is if it's allowed to use the 'MMCSD_BLOCK_SIZE' define to determine the size of the buffer to flush/invalidate. I have tested this implementation for the SDC-interface and so far it works fine.
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Re: Cortex-M7 platform FatFS Cache coherency

Postby steved » Fri Aug 18, 2017 2:25 pm

There are a couple of possible issues here:
1. The heap could be assigned to non-cacheable RAM (especially with Chibi's ability to support multiple memory allocators). So the flushing/invalidating of buffers could be at best a waste of CPU cycles, and at worst a problem.
2. The buffer may not be aligned to cache lines. In that situation I had to flush an extra line - most likely benign when flushing, but potentially problematical when invalidating cache. The preferred fix for this is obviously to ensure the buffer is aligned to a cache line. (Chibi's heap allocator could support this, but at present CH_HEAP_ALIGNMENT is hard-coded into chheap.h. Maybe it should become an overrideable value.)

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Re: Cortex-M7 platform FatFS Cache coherency

Postby Giovanni » Tue Aug 22, 2017 1:13 pm

I think steved is correct, a proper fix would require changes in FatFS because all buffers should be aligned to cache lines.

The best option is to allocate FatFS data in a non-cacheable RAM section.


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