HSI16DIV flag on STM32L0X Topic is solved

[steved]

The STM32L0X series has an optional divide by 4 on the HSI clock which doesn't appear to be supported.
Flag HSI16DIVEN in RCC->CR (HSI16DIVF is read-only status)
The bit is present on all the devices I looked at:
32L011
32L021
32L031
32L041
32L051, 32L052, 32L053
32L062, 32L063
32L071, 32L072, 32L073
32L081, 32L082, 32L083

[Giovanni]

Hi,

Implemented in trunk, if you have a chance, could you give it a try?

Giovanni

[steved]

Done a quick test and my code works as expected (have to remember to update the PLL values as well)