GPIOv2 palEnablePadEvent configures a wrong port

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nclosa
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GPIOv2 palEnablePadEvent configures a wrong port

Postby nclosa » Wed May 20, 2020 2:48 pm

Hi,
The Line palEnablePadEvent(GPIOB, 14U, PAL_EVENT_MODE_FALLING_EDGE), Configure GPIOA.

I think the problem is this:
hal_pal_lld.h in lines 168 and 223:
croff = ((uint32_t)pad & 3U) * 4U; <-- 8U

Néstor

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Re: GPIOv2 palEnablePadEvent configures a wrong port

Postby ticchen » Fri May 22, 2020 5:11 pm

Hi Néstor,

May I know which MCU do you use ?
Taking STM32L0 for example, I checked the STM document RM0377 and Chapter 9.2.4~9.2.7 (SYSCFG_EXTICR),
9.2.4_SYSCFG_EXTICR1.png


I don't think the following code is wrong.
code from: os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c

Code: Select all

  /* Index and mask of the SYSCFG CR register to be used.*/
  cridx  = (uint32_t)pad >> 2U;
  croff = ((uint32_t)pad & 3U) * 4U;
  crmask = ~(0xFU << croff);

  /* Port index is obtained assuming that GPIO ports are placed at regular
     0x400 intervals in memory space. So far this is true for all devices.*/
  portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0xFU;

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Re: GPIOv2 palEnablePadEvent configures a wrong port

Postby nclosa » Fri May 22, 2020 6:16 pm

Hi Ticchen,

I use STM32G071

RM0444 Reference manual
12.5.6 EXTI external interrupt selection register (EXTI_EXTICRx)

Thanks,
Néstor
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ticchen
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Re: GPIOv2 palEnablePadEvent configures a wrong port

Postby ticchen » Fri May 22, 2020 7:20 pm

Hi Néstor,

I tried to search EXTI1_Pos and with 8U size, and the result is:

Code: Select all

$ git grep -l EXTICR1_EXTI1_Pos.*8U | xargs dirname | sort -u
os/common/ext/ST/STM32G0xx
os/common/ext/ST/STM32L5xx


I think ChibiOS need a patch for G0 and L5 series.

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Re: GPIOv2 palEnablePadEvent configures a wrong port

Postby ticchen » Fri May 22, 2020 7:30 pm

Please help to try if this patch works for you

Code: Select all

diff --git a/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c b/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c
index fb7be0a..6f79f7a 100644
--- a/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c
+++ b/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c
@@ -165,7 +165,11 @@ void _pal_lld_enablepadevent(ioportid_t port,
 
   /* Index and mask of the SYSCFG CR register to be used.*/
   cridx  = (uint32_t)pad >> 2U;
+#if STM32_EXTI_TYPE == 0
   croff = ((uint32_t)pad & 3U) * 4U;
+#else
+  croff = ((uint32_t)pad & 3U) * 8U;
+#endif
   crmask = ~(0xFU << croff);
 
   /* Port index is obtained assuming that GPIO ports are placed at regular
@@ -223,7 +227,11 @@ void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) {
 
     /* Index and mask of the SYSCFG CR register to be used.*/
     cridx  = (uint32_t)pad >> 2U;
+#if STM32_EXTI_TYPE == 0
     croff = ((uint32_t)pad & 3U) * 4U;
+#else
+    croff = ((uint32_t)pad & 3U) * 8U;
+#endif
 
     /* Port index is obtained assuming that GPIO ports are placed at regular
        0x400 intervals in memory space. So far this is true for all devices.*/

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Re: GPIOv2 palEnablePadEvent configures a wrong port

Postby nclosa » Fri May 22, 2020 7:54 pm

This works.
Thank you very much.

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Re: GPIOv2 palEnablePadEvent configures a wrong port

Postby Giovanni » Fri May 22, 2020 7:57 pm

Probably crmask should be changed too, it assumes 4 bits. Tomorrow I will give it a try.

Giovanni

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Re: GPIOv2 palEnablePadEvent configures a wrong port

Postby Giovanni » Sun May 24, 2020 8:28 am

After some digging, apparently this is not so simple...

There are various variations in EXTI:

1) It can have the CR register or it can be in SYSCFG (width is 4 or 8 in the two cases).
2) It can have separate raising and falling edge registers on not.

If we look at all STM32 sub-families the two things do not come necessarily together.

So this is what I did:

1) Removed STM32_EXTI_TYPE and replaced it with following:
2) STM32_EXTI_HAS_CR for addressing presence of CR register in EXTI or SYSCFG.
3) STM32_EXTI_SEPARATE_RF for addressing the separate raising and falling edge registers.

Could you give this change a try? I committed it on trunk only, if accepted I will back-port it to stable branches too.

Giovanni

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Re: GPIOv2 palEnablePadEvent configures a wrong port

Postby nclosa » Sun May 24, 2020 1:54 pm

Hi Giovanni,

Done a quick test and my code works as expected.

Thank
Néstor

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Re: GPIOv2 palEnablePadEvent configures a wrong port

Postby alexblack » Mon May 25, 2020 8:20 am

Hi.
STM32G473 project not compiling now. It seems the macro STM32_EXTI_SEPARATE_RF must be FALSE for it.


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