[DEV] STM32G4xx support

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[DEV] STM32G4xx support

Postby Giovanni » Fri Jun 21, 2019 2:07 pm

Lets open the development thread also for the new G4. It looks like a replacement for the ageing F3, interesting device, much higher performance.

Giovanni

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Re: [DEV] STM32G4xx support

Postby JMifune » Mon Jun 24, 2019 12:25 pm

FIR, IIR, Trigonometric accelerator + lot of opamps and ADCs. Looks good.
But I wonder why they have used 12bit ADC and not 16bit from H7?

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Re: [DEV] STM32G4xx support

Postby Giovanni » Tue Jun 25, 2019 5:31 pm

Hi,

Perhaps they wanted to keep it as close as possible to the F3, the ADC should be able to do 16 bits by doing oversampling like the one on L4/L4+.

Giovanni.

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Re: [DEV] STM32G4xx support

Postby JMifune » Sun Aug 11, 2019 3:30 pm

Any updates on G4 support?
It looks really promising for FOC motor control related tasks.
I want to port VESC ESC BLDC controller on G4, it is much more suitable than old F4.
ST itself released small FOC ESC discovery board:
https://www.st.com/content/ccc/resource ... 564746.pdf

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Re: [DEV] STM32G4xx support

Postby Giovanni » Sun Aug 11, 2019 4:21 pm

Hi,

I agree, it is very interesting.

I am waiting for boards, in early September is my guess. Initial support should not take long.

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Re: [DEV] STM32G4xx support

Postby JMifune » Thu Sep 19, 2019 2:41 pm

Giovanni, have you received the boards already?
I got one NUCLEO board and some bare chips couple weeks ago.

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Re: [DEV] STM32G4xx support

Postby Giovanni » Thu Sep 19, 2019 2:58 pm

Hi,

I have the boards, I am looking at the documentation right now, I will start committing some code soon.

Support in OpenOCD would make things easier.

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Re: [DEV] STM32G4xx support

Postby FXCoder » Fri Sep 20, 2019 12:55 pm

Hi,
The last opened windows/Linux set I built for G0 support used a cherry-picked dedicated G0 variant patch that didn't include G4 support.
There is another patch in gerrit which has been in progress for quite some months which modifies the L4 driver to include both G0 and G4.
It isn't through review yet and needs a little more work by the author.
Once that happens I'll cherry-pick that patch and build the Windows and Linux 32/64 openocd set.
I guess that is some weeks off though.
--
Bob
Last edited by FXCoder on Fri Sep 20, 2019 1:35 pm, edited 1 time in total.

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Re: [DEV] STM32G4xx support

Postby Giovanni » Fri Sep 20, 2019 1:18 pm

Hi,

From what I see G4 should be similar to L4+. I started committing G4 code so expect progress, it has some things in common with G0 so work will benefit both ports.

Both G0 and G4 are beautiful, they managed to improve the platforms while keeping that "family feeling".

Giovanni

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Re: [DEV] STM32G4xx support

Postby Giovanni » Sun Sep 22, 2019 9:06 am

Update.

It is progressing well, code is flowing already in the repository.

Just a note, since G4 is the start of a "new generation" I am taking time and do improvements to the general STM32 HAL organization. The problem is the duplication of code caused by ISR sharing in the stm32_isr.c files, each time it takes time and it is source of copy/paste errors.

I am trying to create some kind of mini-drivers for each TIM unit named for example: stm32_tim2.inc. The various stm32_isr.c files will just include the required .inc files making things faster and less error prone.

Ideally I wish to converge toward this organization:
- ISRs and priority-related error checks are no more in each driver but in those .inc files.
- IRQ priorities are in a dedicated section of the mcuconf.h file and not sparse for each unit type.
- Timers with shared IRQs will be fully supported on all platforms (I was holding back on this because the organization problem).

Example:

Code: Select all

/*
    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio

    Licensed under the Apache License, Version 2.0 (the "License");
    you may not use this file except in compliance with the License.
    You may obtain a copy of the License at

        http://www.apache.org/licenses/LICENSE-2.0

    Unless required by applicable law or agreed to in writing, software
    distributed under the License is distributed on an "AS IS" BASIS,
    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    See the License for the specific language governing permissions and
    limitations under the License.
*/

/**
 * @file    TIMv1/stm32_tim1_tim15_tim16_tim17.inc
 * @brief   Shared TIM1, TIM15, TIM16, TIM17 handler.
 *
 * @addtogroup STM32_TIM1_TIM15_TIM16_TIM17_HANDLER
 * @{
 */

/*===========================================================================*/
/* Driver local definitions.                                                 */
/*===========================================================================*/

/**
 * @brief   IRQ vectors initialization.
 */
#define STM32_TIM1_TIM15_TIM16_TIM17_INIT() do {                            \
  nvicEnableVector(STM32_TIM1_BRK_TIM15_NUMBER,                             \
                   STM32_IRQ_TIM1_BRK_TIM15_PRIORITY);                      \
  nvicEnableVector(STM32_TIM1_UP_TIM16_NUMBER,                              \
                   STM32_IRQ_TIM1_UP_TIM16_PRIORITY);                       \
  nvicEnableVector(STM32_TIM1_TRGCO_TIM17_NUMBER,                           \
                   STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY);                    \
  nvicEnableVector(STM32_TIM1_CC_NUMBER,                                    \
                   STM32_IRQ_TIM1_CC_PRIORITY);                             \
} while (0)

/**
 * @brief   IRQ vectors de-initialization.
 */
#define STM32_TIM1_TIM15_TIM16_TIM17_DEINIT() do {                          \
  nvicDisableVector(STM32_TIM1_BRK_TIM15_NUMBER);                           \
  nvicDisableVector(STM32_TIM1_UP_TIM16_NUMBER);                            \
  nvicDisableVector(STM32_TIM1_TRGCO_TIM17_NUMBER);                         \
  nvicDisableVector(STM32_TIM1_CC_NUMBER);                                  \
} while (0)

/*===========================================================================*/
/* Derived constants and error checks.                                       */
/*===========================================================================*/

#if !defined(STM32_IRQ_TIM1_BRK_TIM15_PRIORITY)
#error "STM32_IRQ_TIM1_BRK_TIM15_PRIORITY not defined in mcuconf.h"
#endif

#if !defined(STM32_IRQ_TIM1_UP_TIM16_PRIORITY)
#error "STM32_IRQ_TIM1_UP_TIM16_PRIORITY not defined in mcuconf.h"
#endif

#if !defined(STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY)
#error "STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY not defined in mcuconf.h"
#endif

#if !defined(STM32_IRQ_TIM1_CC_PRIORITY)
#error "STM32_IRQ_TIM1_CC_PRIORITY not defined in mcuconf.h"
#endif

#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_BRK_TIM15_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_BRK_TIM15_PRIORITY"
#endif

#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_UP_TIM16_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_UP_TIM16_PRIORITY"
#endif

#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY"
#endif

#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_CC_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_CC_PRIORITY"
#endif

/*===========================================================================*/
/* Driver exported variables.                                                */
/*===========================================================================*/

/*===========================================================================*/
/* Driver local variables.                                                   */
/*===========================================================================*/

/*===========================================================================*/
/* Driver local functions.                                                   */
/*===========================================================================*/

/*===========================================================================*/
/* Driver interrupt handlers.                                                */
/*===========================================================================*/

#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
/**
 * @brief   TIM1-BRK, TIM15 interrupt handler.
 *
 * @isr
 */
OSAL_IRQ_HANDLER(STM32_TIM1_BRK_TIM15_NUMBER) {

  OSAL_IRQ_PROLOGUE();

#if HAL_USE_GPT
#if STM32_GPT_USE_TIM15
  gpt_lld_serve_interrupt(&GPTD15);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM15
  icu_lld_serve_interrupt(&ICUD15);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM15
  pwm_lld_serve_interrupt(&PWMD15);
#endif
#endif

  OSAL_IRQ_EPILOGUE();
}

/**
 * @brief   TIM1-UP, TIM16 interrupt handler.
 *
 * @isr
 */
OSAL_IRQ_HANDLER(STM32_TIM1_UP_TIM16_NUMBER) {

  OSAL_IRQ_PROLOGUE();

#if HAL_USE_GPT
#if STM32_GPT_USE_TIM1
  gpt_lld_serve_interrupt(&GPTD1);
#endif
#if STM32_GPT_USE_TIM16
  gpt_lld_serve_interrupt(&GPTD16);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM1
  icu_lld_serve_interrupt(&ICUD1);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM1
  pwm_lld_serve_interrupt(&PWMD1);
#endif
#if STM32_PWM_USE_TIM16
  pwm_lld_serve_interrupt(&PWMD16);
#endif
#endif

  OSAL_IRQ_EPILOGUE();
}

/**
 * @brief   TIM1-TRG-COM, TIM17 interrupt handler.
 *
 * @isr
 */
OSAL_IRQ_HANDLER(STM32_TIM1_TRGCO_TIM17_NUMBER) {

  OSAL_IRQ_PROLOGUE();

#if HAL_USE_GPT
#if STM32_GPT_USE_TIM17
  gpt_lld_serve_interrupt(&GPTD17);
#endif
#endif
#if HAL_USE_ICU
  /* Not used by ICU.*/
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM17
  pwm_lld_serve_interrupt(&PWMD17);
#endif
#endif

  OSAL_IRQ_EPILOGUE();
}

/**
 * @brief   TIM1-CC interrupt handler.
 *
 * @isr
 */
OSAL_IRQ_HANDLER(STM32_TIM1_CC_NUMBER) {

  OSAL_IRQ_PROLOGUE();

#if HAL_USE_GPT
  /* Not used by GPT.*/
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM1
  icu_lld_serve_interrupt(&ICUD1);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM1
  pwm_lld_serve_interrupt(&PWMD1);
#endif
#endif

  OSAL_IRQ_EPILOGUE();
}
#endif /* HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM */

/*===========================================================================*/
/* Driver exported functions.                                                */
/*===========================================================================*/

/** @} */


Giovanni


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