[INFO] Solution for shared IRQs on STM32

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[INFO] Solution for shared IRQs on STM32

Postby Giovanni » Sat Jan 05, 2019 12:57 pm

Hi,

An update on this topic.

Shared IRQ prevented us to implement GPT, ICU and PWM on all available timers because shared IRQs. Gradual changes were done to the STM32 HAL in order to address this and now we have a first example of the new infrastructure.

Support for TIM15, TIM16 and TIM17 has been added on STM32F3, L4 and L4++.

This is how it works:
- The file stm32_isr.h declares suppression macros for regular ISRs into HAL LLD drivers.
- The file stm32_isr.c implements new ISRs handling conflicts for the specific platform.
- In mcuconf.h priority settings for shared IRQs are not under the usual GPT, ICU and PWM sections, there is a new "IRQ system settings" section for shared handlers.
- The ST driver does not use this new system, it needs to use timers with non-shared IRQs (not an issue, most logical choices are TIM2, TIM5, TIM6 and TIM7).

Now it is possible to use the same system for all timers on all platforms, it will be gradually extended.

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Re: [INFO] Solution for shared IRQs on STM32

Postby FXCoder » Sun Jan 27, 2019 7:01 am

Hi,
Minor typo fix...

Code: Select all

Index: stm32_isr.c
===================================================================
--- stm32_isr.c   (revision 12602)
+++ stm32_isr.c   (working copy)
@@ -18,7 +18,7 @@
  * @file    STM32L4xx+/stm32_isr.h
  * @brief   STM32L4xx+ ISR handler code.
  *
- * @addtogroup SRM32L4xxp_ISR
+ * @addtogroup STM32L4xxp_ISR
  * @{
  */
 


Also for F4 series are you planning that soon?
I would like to have TIM12 in the official trunk so could have a go at F4 series in the next week or so if that would help.
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Re: [INFO] Solution for shared IRQs on STM32

Postby Giovanni » Sun Jan 27, 2019 7:20 am

Hi,

Just follow the pattern, the main problem is reworking mcuconf files for those devices that do not have yet an updater tool.

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Re: [INFO] Solution for shared IRQs on STM32

Postby FXCoder » Sun Jan 27, 2019 2:16 pm

Hi,
F413 is done and compiles (will test on NUCLEO tomorrow).
As well as stm32_is2.c/h and mcuconf.h changes there are also vector and number entries to be added to stm32_registry.c
Will continue for remainder of F4 during the week.
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Re: [INFO] Solution for shared IRQs on STM32

Postby FXCoder » Mon Jan 28, 2019 2:15 pm

Hi,
Have completed the updates in F4 HAL TIMv1 and the F4/F2 demo files mcuconf.
There is a compile issue I haven't solved.
If either TIM10 or TIM13 are used in GPT there is a compile error "GPTD10/GPTD13 undeclared".
It's late in AU so I'll just post the archive of patches + notes and maybe you can see immediately what's wrong.
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Re: [INFO] Solution for shared IRQs on STM32

Postby Giovanni » Sat Feb 02, 2019 1:38 pm

Hi,

I applied the quality patches but those related to TIMs are too incomplete:

- Not all timer settings overridden in mcuconf, only those of the shared timers, we cannot have half one way and half the other way.
- Missing definition guards in stm32_isr.h.
- Not all mcuconf files fixed, there are a lot also under testhal.

I prefer to make first the updater tool for F4 then proceed with this.

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Re: [INFO] Solution for shared IRQs on STM32

Postby FXCoder » Sat Feb 02, 2019 2:24 pm

Hi,
No problem.
1. I thought I had followed the L4+ pattern which has only the shared timers in the system IRQ section of mcuconf.
So L4+ demo has also to be updated?

2. OK on missing guards.

3. OK. I missed the testhal.

Agreed updater will make things easier.

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Re: [INFO] Solution for shared IRQs on STM32

Postby Giovanni » Sat Feb 02, 2019 2:32 pm

Ops, you are right, it is that way also on L4, no need to make more changes.

I will make updater tools for the F4 first, no need to modify mcuconfs.

Giovanni


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