Hi,
it would be great to have Independent Virtual Timers and ST based on STM32L0/L1/L4 TIM with LSE clock source to get precise time in low power modes.
There is a problem with time measurement with general ST based on 32bit TIM with HSI/MSI clock source due to instability of frequency and delays in low power mode clock source switching (and threads switching as well), it suits well for general purpose but not for precise time measurements used e.g. in LORA applications.
So what do you think about this feature?
Independent Virtual Timers and ST
- Giovanni
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Re: Independent Virtual Timers and ST
Hi,
By "independent" you mean in addition to normal virtual timers?
Giovanni
By "independent" you mean in addition to normal virtual timers?
Giovanni
Re: Independent Virtual Timers and ST
Hi,
yes, virtual timers working independent from ST.
Simplest and weird implementation for stm32l1 on tim11 (LSE clock) attached.
Start timer on first VT and stop timer on empty VTs list has not been added yet (to support lowest power consumption)
yes, virtual timers working independent from ST.
Simplest and weird implementation for stm32l1 on tim11 (LSE clock) attached.
Start timer on first VT and stop timer on empty VTs list has not been added yet (to support lowest power consumption)
- Attachments
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- chivt.zip
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Vitaly
Re: Independent Virtual Timers and ST
quote from stm32l1 RM:
Clock-independent system clock sources for TIM9/TIM10/TIM11
In a number of applications using the 32.768 kHz clock as a time base for the RTC, it is interesting to have time bases that work completely independently of the system clock. This allows the scheduling of tasks without having to take into account the processor state (the processor may be stopped or executing at low, medium or full speed).
For this purpose, the LSE clock is internally redirected to the 3 timers’ ETR inputs, which are used as additional clock sources, as shown in Figure 17 on page 137. This gives up to three independent time bases (using the auto-reload feature) with 1 or 2 compare additional channels for fractional events. For instance, the TIM9’s auto-reload interrupt can be programmed for a 1 second tick interrupt with an additional interrupt occurring 250 ms after the main tick.
Clock-independent system clock sources for TIM9/TIM10/TIM11
In a number of applications using the 32.768 kHz clock as a time base for the RTC, it is interesting to have time bases that work completely independently of the system clock. This allows the scheduling of tasks without having to take into account the processor state (the processor may be stopped or executing at low, medium or full speed).
For this purpose, the LSE clock is internally redirected to the 3 timers’ ETR inputs, which are used as additional clock sources, as shown in Figure 17 on page 137. This gives up to three independent time bases (using the auto-reload feature) with 1 or 2 compare additional channels for fractional events. For instance, the TIM9’s auto-reload interrupt can be programmed for a 1 second tick interrupt with an additional interrupt occurring 250 ms after the main tick.
Vitaly
- Giovanni
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Re: Independent Virtual Timers and ST
This is very interesting, at very least the ST driver should support LSE as clock source.
Anyway, in trunk there is an "alternate" virtual timers implementation under /os/hal/osal/lib, it is used for RTOS-less OSALs but it can be used also standalone. It needs some symbol names changes because some names conflicts with RT symbols.
Giovanni
Anyway, in trunk there is an "alternate" virtual timers implementation under /os/hal/osal/lib, it is used for RTOS-less OSALs but it can be used also standalone. It needs some symbol names changes because some names conflicts with RT symbols.
Giovanni
Re: Independent Virtual Timers and ST
Hi,
support LSE as clock source for ST is great, but there is no 32bit timer with LSE clock source so there is no way to get really long sleep with 1ms tick.
If only implement ST driver with support speeded RTC as timer.
support LSE as clock source for ST is great, but there is no 32bit timer with LSE clock source so there is no way to get really long sleep with 1ms tick.
If only implement ST driver with support speeded RTC as timer.
Vitaly
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