Dynamic core clocking

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A319
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Dynamic core clocking

Postby A319 » Sat Dec 26, 2015 10:22 am

Hi,

When ChibiOS 2.6 has been released, there has been a discussion about dynamic core clocking. viewtopic.php?f=3&t=507

Since my STM32F4 does take a lot of current (~100mA @180MHz), I want to clock it down once I don't need so much calculation power. I know, I can also reduce the current by switching off Ports and functionality, which I don't use, but I want to go further.

I want to know if something has been done since 2012, because I couldn't find any note about the clock in the changelog
...and since macros like MS2ST() would be affected, I don't think it's supported. Am I'm right, or did I miss something? :geek:

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Sven

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Giovanni
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Re: Dynamic core clocking

Postby Giovanni » Sat Dec 26, 2015 10:27 am

Hi,

You can achieve that by changing the AHB divider value, that will allow you to change your system clock dynamically.

Unfortunately the F4 derives all its clocks from the AHB clock so ALL peripherals will be affected. This is not something that can be addressed at SW level.

Newer devices like L0, L4 and F7 allow to clock communication peripherals from another source, this means that changing the AHB divider does not affect them, the scenario is supported in their HAL.

This is true for communication peripherals only, for some reason they didn't do the same for timers, timers are still affected with the exception of LPTIMx which has a separate clock.

Giovanni

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Re: Dynamic core clocking

Postby A319 » Sat Dec 26, 2015 10:39 am

Hi Giovanni,

Thanks for the quick answer. I also thought about the L4 series. As you might know, I'm interested in the camera stuff. But unfortunately I've already done my PCB, so I will consider this for my next version. :)
BTW. That's my project https://github.com/DL7AD/pecanpico7/

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Sven

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Giovanni
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Re: Dynamic core clocking

Postby Giovanni » Sat Dec 26, 2015 10:45 am

On the F4 you are impacted on those peripherals that take their clock from AHB. You may prepare configurations for the full clock state and reduced clock state. All you need to do is to stop peripherals, change clock and then start them again with another configuration.

You may also ignore SPIs and I2Cs, those would still operate at a reduced clock, the problem is mainly with USARTs and timers.

Giovanni

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Re: Dynamic core clocking

Postby pito » Tue Dec 29, 2015 11:24 am

With F4 you may derive the clock for ie. "tick" timer etc. from the external source, ie. from main xtal oscillator (from its output pin). Thus the timer's clock will not change when you switch from 168MHz to the xtal's base freq (or any other freq.)..

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Re: Dynamic core clocking

Postby Koen » Thu Dec 31, 2015 6:42 pm

Hello,

are there limitations or code changes required *in* ChibiOS for dynamic core clocking to work ? For example : clock sources, frequencies and dividers are defined at compile-time in mcuconf.h, is there a risk that ChibiOS will try to use the previously defined STM32_SYSCLK after I've changed the clocking settings ?

In other words : at compile time, the system is set to clock PLL from HSE to give a final system frequency of 216MHz. This is compile-time defined. If I then reconfigure the clocks to PLL from HSI for a frequency of 48MHz, will ChibiOS still try to use the now wrong HSE/216MHz compile-time defines somewhere in the code ?

Thank you !

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Re: Dynamic core clocking

Postby Giovanni » Thu Dec 31, 2015 6:55 pm

Hi,

In the HAL clocking settings are static, this means that the HAL and the OS will continue to use the same settings even after the scaling.

This is not as bad as it sounds, RT timeouts will be longer in proportion and the system time will be proportionally slower but in a predictable way, you can plan for that. Most peripherals can use unaffected clock sources on the F7 so there is no problem with those. Timers will scale down with the CPU however.

Giovanni


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