[TALK] Problems with Cortex-M7

[Giovanni]

I added an article explaining what we discussed here: http://chibios.org/dokuwiki/doku.php?id ... _dma_guide

Giovanni

[alex31]

Code: Select all

  for (i = 0; i < SPI_BUFFERS_SIZE; i++)
    txbuf[i] = (uint8_t)i;
  dmaBufferFlush(txbuf, SPI_BUFFERS_SIZE);
 
  /* Slave selection and data exchange.*/
  spiSelect(&SPID2);
  spiExchange(&SPID2, SPI_BUFFERS_SIZE, txbuf, rxbuf);
  spiUnselect(&SPID2);
 
  /* Invalidating cache over the buffer then checking the
     loopback result.*/
  dmaBufferInvalidate(rxbuf, SPI_BUFFERS_SIZE);

Would it be possible to have some define in mcuconf.h, like SPI2_USE_DMA_VALIDATION (you see the meaning) so that
dmaBufferFlush is called before doing the spiExchange and spiWrite, and dmaBufferInvalidate is called after spiExchange and spiRead
in the driver, so that would transparent to the user ?

there would only be the 32 bytes alignment that should be explicitly done by the programmer, and that alignment could be checked at runtime
in case of the SPI2_USE_DMA_VALIDATION macro is set when check is done, raising an abort if alignment is not respected (and the bug will be found/fix quickly)

otherwise, i know that i will do for myself a function helper that will do that for me because sometime i will forget a flush or an invalidate,
leading to hours of stupid debugging (yes, i begin to know me ...)

Alexandre --

[Giovanni]

That was the initial idea but buffers must be aligned so it is not possible to make it entirely transparent to the user.

Giovanni

[alex31]

Of course buffer(s) has to be declared with this 32 bytes alignment, but the calls to the api are transparent, and if the programmer forgot to align the buffers, you can easily test that the buffers addresses are correctly aligned, and if not, abort (when CH_DBG_ENABLE_ASSERTS is set). Furthermore, the dma functions will be called errorless.

In the no_transparent way, the user has the burden to call the dma flush api, nothing will detect if it's not done correctly and nothing will detect if the buffer(s) is(are) not aligned.

Have pity of a poor teacher who must supervise practical work sessions with generation Y students )

Alexandre

[Giovanni]

I would avoid the F7 for students, everything else is almost equal to the F4 with some extra performance on top.

Giovanni

[alex31]

Well, for now we stay on F4, but for some complicated kind of kalman filter, IKF and IUKF, the extra performance
of the F7 would be welcome. In fact, we will wait a little bit more when stmicro will put 64 bits FPU in the F7 line, because
more than raw power, we need double float FPU to improve numerical stability of some class filters which tend to diverge easily.

That will leave you time to reconsider providing a dumbproof api for programmers with head in the clouds like me

Alexandre

[barthess]

In fact, we will wait a little bit more when stmicro will put 64 bits FPU in the F7 line

Are such MCUs already announced?

[Giovanni]

In fact, we will wait a little bit more when stmicro will put 64 bits FPU in the F7 line

Are such MCUs already announced?

Not yet but I think that the F7 is a device just meant to be a direct upgrade for the F4 (it is almost equal except the core). I would be surprised if they are not working on something much more poweful.

Giovanni

[barthess]

Meh... this F7 looks like draft series. Needs strange works around caches, DMA, ART. Has single precision FPU instead of double. Etc...

[Giovanni]

The cache handling thing is not specific of the F7, apparently it is not handled by the ARM core.

It is strange that they didn't leverage the double precision FPU. The only reason I can think of are erratas in the early M7.

Giovanni