[TALK] Problems with Cortex-M7

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Davide2
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Re: [TALK] Problems with Cortex-M7

Postby Davide2 » Wed Apr 26, 2017 9:01 pm

Hello, if cache invalidation for DMA is handled by the user, are there any issues or disadvantages to merge the ram3 zone with ram1 and ram2 into a contiguous ram0 ?

From :
ram0 : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */
ram1 : org = 0x20020000, len = 368k /* SRAM1 */
ram2 : org = 0x2007C000, len = 16k /* SRAM2 */
ram3 : org = 0x20000000, len = 128k /* DTCM-RAM */
ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */


To :
ram0 : org = 0x20000000, len = 512k /* SRAM1 + SRAM2 + DTCM-RAM */
ram1 : org = 0x20020000, len = 368k /* SRAM1 */
ram2 : org = 0x2007C000, len = 16k /* SRAM2 */
ram3 : org = 0x20000000, len = 128k /* DTCM-RAM */
ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */


Thank you !!

steved
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Re: [TALK] Problems with Cortex-M7

Postby steved » Wed Apr 26, 2017 9:40 pm

Davide2 wrote:Hello, if cache invalidation for DMA is handled by the user, are there any issues or disadvantages to merge the ram3 zone with ram1 and ram2 into a contiguous ram0 ?

The DTCM RAM (ram3) is never cached (by design), so its best used for variables where caching is a definite disadvantage (e.g. DMA-accessed RAM) - not sure about invalidating cache, but flushing cache will definitely take some processor time. I therefore suggest it is far better to manually assign variables to the ram3 zone, otherwise you could end up doing cache operations on uncacheable memory - probably harmless, but unnecessary, and may confuse someone in the future.

Davide2
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Re: [TALK] Problems with Cortex-M7

Postby Davide2 » Thu Apr 27, 2017 6:26 pm

Thank you for the answer.

Somewhat related question : I had ICache and DCache completely disabled. I had a DMA buffer in RAM3 for SDMMC1 aligned to 32 bytes. It did unaligned read sometimes. It worked fine. I re-enabled ICache/DCache and things went wrong when the reads where unaligned. How is this related as, if I understand correctly, these shouldn't impact RAM3 ?

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Giovanni
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Re: [TALK] Problems with Cortex-M7

Postby Giovanni » Thu Apr 27, 2017 7:09 pm

Hi,

Have you read this article?

http://www.chibios.org/dokuwiki/doku.ph ... _dma_guide

It is all about the cache line size, buffers much be aligned in order to not corrupt adjacent data when invalidating the cache.

Giovanni

Davide2
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Joined: Wed Apr 26, 2017 8:52 pm

Re: [TALK] Problems with Cortex-M7

Postby Davide2 » Thu Apr 27, 2017 8:09 pm

Hello,

I did but as DTCM is never cached, how could it affect it ?

Davide2
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Joined: Wed Apr 26, 2017 8:52 pm

Re: [TALK] Problems with Cortex-M7

Postby Davide2 » Fri Apr 28, 2017 12:45 am

I found this :
DTCM-RAM not accessible in read when the MCU is in Sleep mode (WFI/WFE)

Description
• The DTCM-RAM is not accessible in read during Sleep mode (when the CPU clock is
gated). When a read access to the DTCM-RAM is performed by an AHB bus master
(that are the DMAs) while the CPU is in sleep mode (CPU clock is gated), the data is
not transmitted to the AHB bus and the AHB master reads 0x0000_0000.
• There is no issue when a write is performed to the DTCM-RAM while the CPU is in
sleep mode, the data is correctly written in the DTCM-RAM.
Workaround
Use the AXI SRAM1 or SRAM2 for DMA data read transfers and use the AXI DTCM-RAM
for DMA data write transfers in Sleep mode.

http://www.st.com/content/ccc/resource/ ... 257543.pdf


And this :
If the DTCM-RAM is used as data location and the variables used are byte or/and halfword
types, since there is no ECC management in this RAM on the STM32F7 Series, it is
recommended to disable the read-modify-write of the DTCM-RAM in the DTCM interface (in
the DTCMCR register) to increase the performance.
To do this, add the following C code in SystemInit() in system_stm32f7xx.c file or at the
beginning of the main function:
__IO uint32_t * CM7_DTCMCR = (uint32_t*)(0xE000EF94);
* CM7_DTCMCR &= 0xFFFFFFFD; /* Disable read-modify-write */

http://www.st.com/content/ccc/resource/ ... 169764.pdf


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