[INFO] Solution for shared IRQs on STM32

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[INFO] Solution for shared IRQs on STM32

Postby Giovanni » Sat Jan 05, 2019 12:57 pm


An update on this topic.

Shared IRQ prevented us to implement GPT, ICU and PWM on all available timers because shared IRQs. Gradual changes were done to the STM32 HAL in order to address this and now we have a first example of the new infrastructure.

Support for TIM15, TIM16 and TIM17 has been added on STM32F3, L4 and L4++.

This is how it works:
- The file stm32_isr.h declares suppression macros for regular ISRs into HAL LLD drivers.
- The file stm32_isr.c implements new ISRs handling conflicts for the specific platform.
- In mcuconf.h priority settings for shared IRQs are not under the usual GPT, ICU and PWM sections, there is a new "IRQ system settings" section for shared handlers.
- The ST driver does not use this new system, it needs to use timers with non-shared IRQs (not an issue, most logical choices are TIM2, TIM5, TIM6 and TIM7).

Now it is possible to use the same system for all timers on all platforms, it will be gradually extended.


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