STM32L4+ support

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Re: STM32L4+ support

Postby FXCoder » Thu Aug 30, 2018 2:17 pm

Giovanni,
We are just laying out a board using a L4R9 UFBGA144 and are routing traces for TIM inputs that support ICU.
In the L4+ TIM15 is suitable for ICU so I am just checking if you planned on adding TIM15 as an ICU option to TIMv1/hal_icu_lld.c/h?
If it helps time wise I could work up the changes and send them.

Thanks

--

Bob

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Re: STM32L4+ support

Postby Giovanni » Thu Aug 30, 2018 3:47 pm

It uses a shared IRQ but TIM1_BRK is not used anywhere, it should be fine. Patches would be OK, just follow the pattern.

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Re: STM32L4+ support

Postby FXCoder » Thu Aug 30, 2018 4:52 pm

Patch...
- TIMv1 ICU additions for TIM15
- Typo in cmparams.h ($ -> 4)
- Added ICU settings to mcuconf.h of demo project

Compiled with ICU enabled w/o error but no test carried out on NUCLEO yet.


Code: Select all

Index: demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h
===================================================================
--- demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h   (revision 12234)
+++ demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h   (working copy)
@@ -74,9 +74,24 @@
  * I2C driver system settings.
  */
 
+
 /*
  * ICU driver system settings.
  */
+#define STM32_ICU_USE_TIM1                  FALSE
+#define STM32_ICU_USE_TIM2                  FALSE
+#define STM32_ICU_USE_TIM3                  FALSE
+#define STM32_ICU_USE_TIM4                  FALSE
+#define STM32_ICU_USE_TIM5                  FALSE
+#define STM32_ICU_USE_TIM9                  FALSE
+#define STM32_ICU_USE_TIM15                 FALSE
+#define STM32_ICU_TIM1_IRQ_PRIORITY         7
+#define STM32_ICU_TIM2_IRQ_PRIORITY         7
+#define STM32_ICU_TIM3_IRQ_PRIORITY         7
+#define STM32_ICU_TIM4_IRQ_PRIORITY         7
+#define STM32_ICU_TIM5_IRQ_PRIORITY         7
+#define STM32_ICU_TIM9_IRQ_PRIORITY         7
+#define STM32_ICU_TIM15_IRQ_PRIORITY        7
 
 /*
  * PWM driver system settings.
Index: os/common/startup/ARMCMx/devices/STM32L4xx/cmparams.h
===================================================================
--- os/common/startup/ARMCMx/devices/STM32L4xx/cmparams.h   (revision 12234)
+++ os/common/startup/ARMCMx/devices/STM32L4xx/cmparams.h   (working copy)
@@ -18,7 +18,7 @@
  * @file    STM32F4xx/cmparams.h
  * @brief   ARM Cortex-M4 parameters for the STM32F4xx.
  *
- * @defgroup ARMCMx_STM32L$xx STM32L4xx Specific Parameters
+ * @defgroup ARMCMx_STM32L4xx STM32L4xx Specific Parameters
  * @ingroup ARMCMx_SPECIFIC
  * @details This file contains the Cortex-M4 specific parameters for the
  *          STM32L4xx platform.
Index: os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c
===================================================================
--- os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c   (revision 12234)
+++ os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c   (working copy)
@@ -94,6 +94,13 @@
 ICUDriver ICUD9;
 #endif
 
+/**
+ * @brief   ICUD15 driver identifier.
+ * @note    The driver ICUD15 allocates the timer TIM15 when enabled.
+ */
+#if STM32_ICU_USE_TIM15 || defined(__DOXYGEN__)
+ICUDriver ICUD15;
+#endif
 /*===========================================================================*/
 /* Driver local variables and types.                                         */
 /*===========================================================================*/
@@ -323,6 +330,27 @@
 #endif /* !defined(STM32_TIM9_SUPPRESS_ISR) */
 #endif /* STM32_ICU_USE_TIM9 */
 
+#if STM32_ICU_USE_TIM15 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM15_SUPPRESS_ISR)
+#if !defined(STM32_TIM15_HANDLER)
+#error "STM32_TIM15_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM15 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM15_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  icu_lld_serve_interrupt(&ICUD15);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* !defined(STM32_TIM15_SUPPRESS_ISR) */
+#endif /* STM32_ICU_USE_TIM15 */
+
 /*===========================================================================*/
 /* Driver exported functions.                                                */
 /*===========================================================================*/
@@ -375,6 +403,12 @@
   icuObjectInit(&ICUD9);
   ICUD9.tim = STM32_TIM9;
 #endif
+
+#if STM32_ICU_USE_TIM15
+  /* Driver initialization.*/
+  icuObjectInit(&ICUD15);
+  ICUD15.tim = STM32_TIM15;
+#endif
 }
 
 /**
@@ -499,6 +533,21 @@
 #endif
     }
 #endif
+
+#if STM32_ICU_USE_TIM15
+    if (&ICUD15 == icup) {
+      rccEnableTIM15(true);
+      rccResetTIM15();
+#if !defined(STM32_TIM15_SUPPRESS_ISR)
+      nvicEnableVector(STM32_TIM15_NUMBER, STM32_ICU_TIM15_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM15CLK)
+      icup->clock = STM32_TIM15CLK;
+#else
+      icup->clock = STM32_TIMCLK2;
+#endif
+    }
+#endif
   }
   else {
     /* Driver re-configuration scenario, it must be stopped first.*/
@@ -650,6 +699,15 @@
       rccDisableTIM9();
     }
 #endif
+
+#if STM32_ICU_USE_TIM15
+    if (&ICUD15 == icup) {
+#if !defined(STM32_TIM15_SUPPRESS_ISR)
+      nvicDisableVector(STM32_TIM15_NUMBER);
+#endif
+      rccDisableTIM15();
+    }
+#endif
   }
 }
 
Index: os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.h
===================================================================
--- os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.h   (revision 12234)
+++ os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.h   (working copy)
@@ -105,6 +105,15 @@
 #endif
 
 /**
+ * @brief   ICUD15 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD15 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_ICU_USE_TIM15) || defined(__DOXYGEN__)
+#define STM32_ICU_USE_TIM15                  FALSE
+#endif
+
+/**
  * @brief   ICUD1 interrupt priority level setting.
  */
 #if !defined(STM32_ICU_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
@@ -152,6 +161,13 @@
 #if !defined(STM32_ICU_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__)
 #define STM32_ICU_TIM9_IRQ_PRIORITY         7
 #endif
+
+/**
+ * @brief   ICUD15 interrupt priority level setting.
+ */
+#if !defined(STM32_ICU_TIM15_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ICU_TIM15_IRQ_PRIORITY         7
+#endif
 /** @} */
 
 /*===========================================================================*/
@@ -186,10 +202,14 @@
 #error "TIM9 not present in the selected device"
 #endif
 
+#if STM32_ICU_USE_TIM15 && !STM32_HAS_TIM15
+#error "TIM9 not present in the selected device"
+#endif
+
 #if !STM32_ICU_USE_TIM1 && !STM32_ICU_USE_TIM2 &&                           \
     !STM32_ICU_USE_TIM3 && !STM32_ICU_USE_TIM4 &&                           \
     !STM32_ICU_USE_TIM5 && !STM32_ICU_USE_TIM8 &&                           \
-    !STM32_ICU_USE_TIM9
+    !STM32_ICU_USE_TIM9 && !STM32_ICU_USE_TIM15
 #error "ICU driver activated but no TIM peripheral assigned"
 #endif
 
@@ -250,6 +270,14 @@
 #endif
 #endif
 
+#if STM32_ICU_USE_TIM15
+#if defined(STM32_TIM15_IS_USED)
+#error "ICUD15 requires TIM15 but the timer is already used"
+#else
+#define STM32_TIM15_IS_USED
+#endif
+#endif
+
 /* IRQ priority checks.*/
 #if STM32_ICU_USE_TIM1 && !defined(STM32_TIM1_SUPPRESS_ISR) &&              \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM1_IRQ_PRIORITY)
@@ -286,6 +314,11 @@
 #error "Invalid IRQ priority assigned to TIM9"
 #endif
 
+#if STM32_ICU_USE_TIM15 && !defined(STM32_TIM15_SUPPRESS_ISR) &&              \
+    !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM15_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM9"
+#endif
+
 /*===========================================================================*/
 /* Driver data structures and types.                                         */
 /*===========================================================================*/
@@ -464,6 +497,10 @@
 extern ICUDriver ICUD9;
 #endif
 
+#if STM32_ICU_USE_TIM15 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD15;
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif

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Re: STM32L4+ support

Postby Giovanni » Mon Sep 10, 2018 1:35 pm

FXCoder wrote:Giovanni.
Here is a quick hack W64 build of openocd that will at least get you running with L4+ testing.
I built it using Liviu Ionescu's GNU MCU build system for openocd.


I tried it, it fails stating that cannot erase sectors even if I erase the chip beforehand.

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Re: STM32L4+ support

Postby FXCoder » Tue Sep 11, 2018 5:34 am

Apologies.
I didn't make it clear that the basic idea was to get debug working as an interim measure while openocd sector erase gets sorted.
So either...
1. program using ST-LINK (a bit tedious) and then run from Eclipse (with load image turned off)
OR
2. flash from the Run Commands section (again with load image turned off)
Here is the clunky hack to put in Run Commands to at least get going...

Code: Select all

monitor flash probe 0
monitor stm32l4x mass_erase 0
monitor flash write_image C:/ChibiStudio/chibios_trunk/demos/STM32/RT-STM32L4R5ZI-NUCLEO144/build/ch.elf


You might have a better interim solution....

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Re: STM32L4+ support

Postby faisal » Tue Sep 11, 2018 2:03 pm

Have you tried using the segger GDB Server, or STLink?

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Re: STM32L4+ support

Postby Giovanni » Tue Sep 11, 2018 5:44 pm

I will try Segger too. Does ST-Link have a GDB server? I don't think so.

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Re: STM32L4+ support

Postby Giovanni » Sat Sep 15, 2018 8:20 am

The demo starts using the patched OpenOCD (there are strange random problems with flashing, you may need to power off the board at times). Timings looks correct so the clock tree is working, it is not really different from the normal L4 anyway.

Code: Select all


*** ChibiOS/RT Test Suite
***
*** Compiled:     Sep 15 2018 - 09:35:42
*** Platform:     STM32L4+ Ultra Low Power
*** Test Board:   STMicroelectronics STM32 Nucleo144-L4R5ZI

============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture:                       ARMv7E-M
--- Core Variant:                       Cortex-M4
--- Compiler:                           GCC 7.3.1 20180622 (release) [ARM/embedded-7-branch revision 261907]
--- Port Info:                          Advanced kernel mode
--- Natural alignment:                  4
--- Stack alignment:                    8
--- Working area alignment:             8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (Kernel Info)
--- Product:                            ChibiOS/RT
--- Stable Flag:                        0
--- Version String:                     6.0.0
--- Major Number:                       6
--- Minor Number:                       0
--- Patch Number:                       0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (Kernel Settings)
--- CH_CFG_ST_RESOLUTION:               32
--- CH_CFG_ST_FREQUENCY:                10000
--- CH_CFG_INTERVALS_SIZE:              32
--- CH_CFG_TIME_TYPES_SIZE:             32
--- CH_CFG_ST_TIMEDELTA:                2
--- CH_CFG_TIME_QUANTUM:                0
--- CH_CFG_MEMCORE_SIZE:                0
--- CH_CFG_NO_IDLE_THREAD:              0
--- CH_CFG_OPTIMIZE_SPEED:              1
--- CH_CFG_USE_TM:                      1
--- CH_CFG_USE_REGISTRY:                1
--- CH_CFG_USE_WAITEXIT:                1
--- CH_CFG_USE_SEMAPHORES:              1
--- CH_CFG_USE_SEMAPHORES_PRI:          0
--- CH_CFG_USE_MUTEXES:                 1
--- CH_CFG_USE_MUTEXES_RECURS:          0
--- CH_CFG_USE_CONDVARS:                1
--- CH_CFG_USE_CONDVARS_TIMEO:          1
--- CH_CFG_USE_EVENTS:                  1
--- CH_CFG_USE_EVENTS_TIMEOUT:          1
--- CH_CFG_USE_MESSAGES:                1
--- CH_CFG_USE_MESSAGES_PRI:            0
--- CH_CFG_USE_MAILBOXES:               1
--- CH_CFG_USE_MEMCORE:                 1
--- CH_CFG_USE_HEAP:                    1
--- CH_CFG_USE_MEMPOOLS:                1
--- CH_CFG_USE_OBJ_FIFOS:               1
--- CH_CFG_USE_DYNAMIC:                 1
--- CH_CFG_USE_FACTORY:                 1
--- CH_CFG_FACTORY_MAX_NAMES_LENGTH:    8
--- CH_CFG_FACTORY_OBJECTS_REGISTRY:    1
--- CH_CFG_FACTORY_GENERIC_BUFFERS:     1
--- CH_CFG_FACTORY_SEMAPHORES:          1
--- CH_CFG_FACTORY_MAILBOXES:           1
--- CH_CFG_FACTORY_OBJ_FIFOS:           1
--- CH_DBG_STATISTICS:                  0
--- CH_DBG_SYSTEM_STATE_CHECK:          0
--- CH_DBG_ENABLE_CHECKS:               0
--- CH_DBG_ENABLE_ASSERTS:              0
--- CH_DBG_TRACE_MASK:                  255
--- CH_DBG_TRACE_BUFFER_SIZE:           128
--- CH_DBG_ENABLE_STACK_CHECK:          0
--- CH_DBG_FILL_THREADS:                0
--- CH_DBG_THREADS_PROFILING:           0
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (System layer and port interface)
----------------------------------------------------------------------------
--- Test Case 2.1 (System integrity functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Critical zones functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Interrupts handling functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.4 (System Tick Counter functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Threads Functionality)
----------------------------------------------------------------------------
--- Test Case 3.1 (Thread Sleep functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Ready List functionality, threads priority order)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.3 (Priority change test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.4 (Priority change test with Priority Inheritance)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Suspend/Resume)
----------------------------------------------------------------------------
--- Test Case 4.1 (Suspend and Resume functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Counter Semaphores)
----------------------------------------------------------------------------
--- Test Case 5.1 (Semaphore primitives, no state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 5.2 (Semaphore enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 5.3 (Semaphore timeout test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 5.4 (Testing chSemAddCounterI() functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 5.5 (Testing chSemWaitSignal() functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 5.6 (Testing Binary Semaphores special case)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Mutexes, Condition Variables and Priority Inheritance)
----------------------------------------------------------------------------
--- Test Case 6.1 (Priority enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.2 (Priority return verification)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.3 (Repeated locks, non recursive scenario)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.4 (Condition Variable signal test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.5 (Condition Variable broadcast test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.6 (Condition Variable priority boost test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Synchronous Messages)
----------------------------------------------------------------------------
--- Test Case 7.1 (Messages Server loop)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Event Sources and Event Flags)
----------------------------------------------------------------------------
--- Test Case 8.1 (Events registration)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.2 (Event Flags dispatching)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.3 (Events Flags wait using chEvtWaitOne())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.4 (Events Flags wait using chEvtWaitAny())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.5 (Events Flags wait using chEvtWaitAll())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.6 (Events Flags wait timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.7 (Broadcasting using chEvtBroadcast())
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Dynamic threads)
----------------------------------------------------------------------------
--- Test Case 9.1 (Threads creation from Memory Heap)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Threads creation from Memory Pool)
--- Result: SUCCESS
============================================================================
=== Test Sequence 10 (Benchmarks)
----------------------------------------------------------------------------
--- Test Case 10.1 (Messages performance #1)
--- Score : 576892 msgs/S, 1153784 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.2 (Messages performance #2)
--- Score : 465093 msgs/S, 930186 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.3 (Messages performance #3)
--- Score : 465091 msgs/S, 930182 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.4 (Context Switch performance)
--- Score : 1821528 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.5 (Threads performance, full cycle)
--- Score : 339919 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.6 (Threads performance, create/exit only)
--- Score : 439531 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.7 (Mass reschedule performance)
--- Score : 148691 reschedules/S, 892146 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.8 (Round-Robin voluntary reschedule)
--- Score : 1126700 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.9 (Virtual Timers set/reset performance)
--- Score : 1025724 timers/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.10 (Semaphores wait/signal performance)
--- Score : 2806872 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.11 (Mutexes lock/unlock performance)
--- Score : 1399328 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.12 (RAM Footprint)
--- System: 120 bytes
--- Thread: 68 bytes
--- Timer : 20 bytes
--- Semaph: 12 bytes
--- Mutex : 16 bytes
--- CondV.: 8 bytes
--- EventS: 4 bytes
--- EventL: 20 bytes
--- MailB.: 40 bytes
--- Result: SUCCESS
----------------------------------------------------------------------------

Final result: SUCCESS

*** ChibiOS OS Library Test Suite
***
*** Compiled:     Sep 15 2018 - 09:35:42
*** Platform:     STM32L4+ Ultra Low Power
*** Test Board:   STMicroelectronics STM32 Nucleo144-L4R5ZI

============================================================================
=== Test Sequence 1 (Mailboxes)
----------------------------------------------------------------------------
--- Test Case 1.1 (Mailbox normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (Mailbox I-Class API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (Mailbox timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (Memory Pools)
----------------------------------------------------------------------------
--- Test Case 2.1 (Loading and emptying a memory pool)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Loading and emptying a guarded memory pool without waiting)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Guarded Memory Pools timeout)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Memory Heaps)
----------------------------------------------------------------------------
--- Test Case 3.1 (Allocation and fragmentation)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Default Heap)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Objects Factory)
----------------------------------------------------------------------------
--- Test Case 4.1 (Objects Registry)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.2 (Dynamic Buffers Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.3 (Dynamic Semaphores Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.4 (Dynamic Mailboxes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.5 (Dynamic Objects FIFOs Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------

Final result: SUCCESS


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Re: STM32L4+ support

Postby FXCoder » Sat Sep 15, 2018 10:44 am

Not getting any random problems so far.
Have run test sequence, reset and flashed multiple times.
Running on a -P board but that should make no difference.

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Re: STM32L4+ support

Postby Giovanni » Sat Sep 15, 2018 11:09 am

Probably it is just my setup.

I think this is a great micro, probably the best STM32 overall, I am looking into the other drivers now.

Giovanni


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