I2C clock

ChibiOS public support forum for topics related to the Freescale Kinetis family of micro-controllers.

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fredizzimo
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I2C clock

Postby fredizzimo » Sat Apr 02, 2016 11:17 pm

I'm going to use the I2C support on a MK20DX256VLH7 chip. So I started by looking at the implementation (currently I'm using flabbergast's fork, but now that it's merged I will probably soon start using the contrib version). But I think I found some bugs for the clock setting.

I'm not experience with microcontroller programming, so rather than doing a pull request, I ask more experienced people here first. The code calculates the divisor using the sysclock frequency, but if I'm reading the documentation right it should be the bus frequency. So is this a bug?

The code also doesn't take advantage of the multiplier, which would make it possible to support more exact speeds. Since the SCL divider values are closer together for low values, I think the highest possible divider should be applied first, before trying to find the best fitting value.

Finally the code doesn't expose the fact that you can tune the hold times. I don't know how important that is in practice, but maybe it would be a good idea to let the user be able to set the frequency register manually too if he wants to, for example by making a clock value of 0 a special value, and adding another field to the configuration?

utzig
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Re: I2C clock

Postby utzig » Sat Apr 02, 2016 11:34 pm

fredizzimo wrote:The code calculates the divisor using the sysclock frequency, but if I'm reading the documentation right it should be the bus frequency. So is this a bug?

Hmmm, I can't remember the DS from memory but I would assume sysclock and busclock are the same frequency. If I recall correctly, when I wrote the i2c driver I left some of the clocking things out for simplicity. Will try to check the issues you pointed, tomorrow.

Cheers,
Fabio Utzig

fredizzimo
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Re: I2C clock

Postby fredizzimo » Sat Apr 02, 2016 11:58 pm

If you read the manual section 5.4.1 - "Device clock summary", you can see that the system clock goes up to 72 MHz, while the bus clock only goes to 50 Mhz, so if you want to run full speed the bus clock has to be slower.

I'm running the chip at 72Mhz, and use a 2 divider to get a 36Mhz bus clock, like option 2 in section 5.5.

utzig
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Re: I2C clock

Postby utzig » Mon Apr 04, 2016 12:48 am

Right, our demos seem to all be running with the same sysclk and busclk frequencies so that would "mask" the problem. But I agree with all your points. Go ahead and create a pull request (or one for each change, as you wish...).

Fabio Utzig

flabbergast
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Re: I2C clock

Postby flabbergast » Mon Apr 04, 2016 9:03 am

The current kinetis i2c driver would actually benefit from a slight overhaul: add DMA, implement timeout (ignored in the current implementation); also I ran into a problem when i2cMasterTransmitTimeout is called with 'rxsize' 0 (this is indicated in the ChibiOS docs to be done when transmit is called without an expectation of a reply) - but this may be because the I2C chip I'm playing with does actually respond with more than an ACK even though its datasheet doesn't say so.

I'll coordinate with fredizzimo if/when I'll code anything.

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Re: I2C clock

Postby jstruebel » Sat Apr 09, 2016 3:36 am

I ran into the same problem in the i2cMasterTransmitTimeout, but for my chip I had to fix it or else it wouldn't accept the write that I was performing. I just realized that I made the fix in your old KINETIS branch and didn't copy it over when it moved to Contrib. I just submitted PR53 with my fix. Basically I just test if rxsize > 0 in order to execute the receive logic.

flabbergast
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Re: I2C clock

Postby flabbergast » Tue Apr 19, 2016 10:35 am

I've been playing around with the I2C driver: https://github.com/flabbergast/ChibiOS- ... ts/kinetis

No really substantial changes; I've fixed the clock bug Fred reported, and slightly rewrote the driver itself and added comments - I needed to clear up for myself what's going on where. One of the reasons for the rewrite (basically moved if/else branches around a bit) is to make it easier to work around Freescale's messup of the I2C hardware on KL26Z and (mainly) KL27Z, see here and here. (This hasn't happened yet, so the I2C doesn't work on KL27Z yet.)

I've tested with 24LC256 EEPROM on various platforms (KL25, KL26, K20/MCHCK) and it seems to be doing what's expected.

No DMA yet (I'll probably not be doing that because I have no experience with DMA whatsoever), would be nice if someone else would take a stab at this.

For the extra configuration options (more precise clock selection, hold times, glitch filter and high drive), I would prefer not to put those into the driver itself, and just recommend setting the registers manually in user code, right after calling i2cStart(..). I think the current config_frequency is a reasonable compromise between having a lot of one-call code in the firmware (computing the F register from the given frequency) and having the convenience of specifying the frequency instead of the 'F' register manually. {I've never needed to mess with anything more precise than approximate frequency for I2C devices I've played with, but admittedly it was only about 5 different ones.}


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