ChibiOS Free Embedded RTOS

I was testing the ADC of the STM32H743, and found a few things that could improved in the testhal example.

1. ADC1_IN0 is tied to PA9_C, a dedicated analog pin not available on the nucleo board. To sample PA0 instead replace IN0 by IN16 in .

2. It would be very useful to spit out the ADC values to USART3, so the ADC can actually be tested.

3. Visual feedback of the ADC value could also be a simple way to test, let the pulse-width of the blink depend on the read ADC value.

Attached are the patches for these three points.

I just noticed I missed some changes, changing AN0 to AN16 too. Updated patches attached.

Currently trying to get dual mode ADC working. There seems to be an issue with the DMA.

I made some changes to ADCv4 dual mode, however I didn't manage to get it working yet. The values from the slave ADC (ADC2) are always 0. Not sure if it fails on DMA transfer or on ADC sampling.

Here are the patches of what I have till now.

ADCv4 dual mode fixes according to reference manual:
- DMA tranfser size
- Fix DAMDF
- add ADC_CCR_DUAL_ defines
- H7 REV_V RES fixes

Also modify testhal to test dual mode.

If someone else can have a look I would be happy, I'm not sure what to try next.

piers wrote:1. ADC1_IN0 is tied to PA9_C, a dedicated analog pin not available on the nucleo board. To sample PA0 instead replace IN0 by IN16 in .

IN16 is fine as long is it's single ended, if differential it would also need PA1 which is assigned to ETH_REF_CLK.

Mike

Just having another look at this.

For STM32F4 and F7 series the temperature & VREF values are enabled by:
adcSTM32EnableTSVREFE()

and including something like these SMPR and SQR register settings on ADC1:
ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_480)
ADC_SMPR1_SMP_VREF(ADC_SAMPLE_480)
ADC_SQR2_SQ7_N(ADC_CHANNEL_SENSOR)
ADC_SQR3_SQ6_N(ADC_CHANNEL_VREFINT)

In the code for STM32H7 it has these coded:
adcSTM32EnableVREF(&PORTAB_ADC1);
adcSTM32EnableTS(&PORTAB_ADC1);

However, according to the docs, VSENSE and VREFINT are on pins 18 and 19 of ADC3.

So I think the example needs to change for this (I will take a look if I get a chance), but do I also need the equivalent SMPR & SQR registers set?

Also, for clarity I think there needs to be appropriate values defines in:
ChibiOS_20.3.1/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.h

something like:
#define ADC_CHANNEL_VBAT 17U /**< @brief VBAT. */
#define ADC_CHANNEL_VSENSE 18U /**< @brief VSENSE (Temperature). */
#define ADC_CHANNEL_VREFINT 19U /**< @brief VREFINT. */

Or as a minimum this would be needed:
#define ADC_CHANNEL_IN19 19U

See page 929 of:
https://www.st.com/resource/en/referenc ... ronics.pdf

Mike

Hi,

You should post this kind of things on "bug reports" or "change request", I only look for things to do in those two sections. It is hard to follow all forums for changes.

Giovanni

I'll see if I can get VREFINT and VSENSE using the standard source, then post under bugs with code that works (on the Nucleo144 STMH743 Rev Y).

The changes to dual mode probably need to handled separately, so I will try to look at that after.

Mike

Hi,
I posted my progress on the STM32H7 ADC in a separate thread: viewtopic.php?f=35&t=5576

For using ADC3 you do need those patches, as the bdma implementation was not finished. I can add these defines there too to keep things together.

I only have a STM32H743 Rev V (the newer revision), so if you want you can do some tests on the older Rev Y to see if everything works there as well. Though for everyone doing something serious with the STM32H7 ADC it is probably better to get a new board. (note that for the Rev Y you need to use STM32_ENFORCE_H7_REV_V as the naming is mixed up, see viewtopic.php?f=35&t=5570 In my patches I used STM32_ENFORCE_H7_REV_Y so for now for Rev Y you need to define both STM32_ENFORCE_H7_REV_V and STM32_ENFORCE_H7_REV_Y)