SPIv3 issues

Discussions and support about ChibiOS/HAL, the MCU Hardware Abstraction Layer.
jschall
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Re: SPIv3 issues

Postby jschall » Tue Jan 14, 2020 6:17 am

With my fixes in, I've run into another issue - when setting a higher baud rate, the transfer seems to stall with 0 bytes left in the tx DMA and 1 byte left in the rx DMA. Shouldn't happen because MASRX is set - the SPI peripheral should stop and wait for the rx bytes to be read if the DMA isn't keeping up...

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Giovanni
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Re: SPIv3 issues

Postby Giovanni » Tue Jan 14, 2020 6:22 am

Try giving RX DMA a higher priority than TX, if it is a bandwidth problem this should fix it.

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Re: SPIv3 issues

Postby jschall » Wed Jan 15, 2020 2:57 am

Shouldn't be possible to drop bytes, right?

I'll try what you suggested.

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Giovanni
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Re: SPIv3 issues

Postby Giovanni » Wed Jan 15, 2020 8:43 am

I doubt it is a problem with bandwidth.

One byte left in RX DMA means that SPI stopped requesting a transfer too early, I would also check if there are problems with the RXFIFO settings (threshold).

What is the size of the failing transfer?

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Re: SPIv3 issues

Postby Giovanni » Sun Jan 19, 2020 3:43 pm

I remembered this discussion:

viewtopic.php?f=16&t=4140&start=110#p34911

Could you try the proposed fix? (setting the PPRE divider to 1)? there is something strange going on in HW I think.

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