PWM vs ATMega328p - why TCCR0A and TCCR0B are missing?

[igor]

Hi,
I setup PW generation on an ATMega328p by using direct writes to 4 channels: 0A, 0B, 2A and 2B.
Then I tried to reproduce the same through HAL, but I cannot find references to 0A and 0B.

I am starting to wonder if I'm wrong in thinking that Timer1 is reserved for the tickless OS.
I recall it that way, but I can't find anymore the place where I think I read it.

Do I remember incorrectly and instead it's Timer0 to be reserved?
In both cases, where can I find this piece of configuration?

TIA, igor

[utzig]

Timer 0 is used in periodic mode and Timer 1 in tickless mode.

It is configured in this file: os/hal/ports/AVR/st_lld.c

Cheers,
Fabio Utzig

[igor]

Thanks, I remember seeing it, but I thought it was in the board files.

So, as long as I keep the OS in tickless mode, it seems safe to use Timer0, right?

But it's not supported by the PWM library, as far as I can see.

I can of course continue using direct register access, but if there is a way I could add support for Timer0
that is deemed acceptable (iow mergeable), I do not mind doing it.

igor

[utzig]

The PWM driver was written way before the tickless code, so yeah, there may be issues with timer reuse. If you are in the mood to fix it, I'll say go for it!

[igor]

The problem is that I do not see any solution without drawbacks.
In os/hal/ports/AVR/pwm_lld.c TIM1 refers to Timer1, TIM2 to Timer2.
If I introduce TIM0, that will probably affect the generic files and make the AVR port deviate from the others.
If I make TIM1 refer to Timer0 and shift the others accordingly, it will break whatever existing AVR code might be relying on the PWM driver.
And finally, if I introduce a TIM10 or anyway high enough, and point it to Timer0, it really seems like a hack.

[igor]

One more option, that might solve all the issues I previously listed:
to have TIM1 refer either to Timer0 or Timer1, depending on how the OS is configured.
In case the OS is configured with periodic tic, then Timer0 is in use and TIM1 would refer to to Timer1.
In case the OS is configured to be ticless, then Timer1 is in use and TIM1 would refer to to Timer0.

Would this be acceptable for merging?

[utzig]

The reason the STM32 port has no TIM0 is mainly because the timer names in that family start from one. I see no problem in you creating an AVR_PWM_USE_TIM0 macro. The only reason there is none now is that TIM0 was previously reserved as tick timer much like Systick is for the ARM-Cortexes.

[igor]

Umm, I tried adding support for TIM0 and it's no big deal, but then I'm stuck.

I have been programming the registers directly, to test what I want to achieve:

Code: Select all

  PORTD &= ~(_BV(PD3) | _BV(PD5) | _BV(PD6));
  DDRD |= _BV(PD3) | _BV(PD5) | _BV(PD6);
  PORTB &= ~_BV(PD3);
  DDRB |= _BV(PB3);

 /* Here starts the PWM configuration */
  TCNT0=0;
  TCCR0A = _BV(COM0A1) | _BV(COM0B1) | _BV(WGM01) | _BV(WGM00);
  TCCR0B = _BV(CS01) | _BV(CS00);
  OCR0A = 63;    // PD6  6
  OCR0B = 127;   // PD5  5

  TCNT2=0;
  TCCR2A = _BV(COM2A1) | _BV(COM2B1) | _BV(WGM21) | _BV(WGM20);
  TCCR2B = _BV(CS22);
  OCR2A = 95;    // PB3 11
  OCR2B = 159;   // PD3  3



I don't think I can achieve the same configuration by using the current PWM API, unless I start defining everything through PWM_DRIVER_EXT_FIELDS and ignore the generic part.