strange coherency problem with dma buffer
Posted: Wed Jul 08, 2020 9:20 pm
Hello,
My question is not chibios specific.
I have received a bug report on open source software that i wrote, on a dshot driver which basically fill a buffer which is transmitted (DMA) to a timer in pwm mode to make a pulse coded numeric signal respecting the dshot protocol. The bug report is : 7% of the frames are not correct.
The processor used is a F7, because of cache coherency problem, i took care of putting the global variable buffer in ram3, a ram section which is uncached, so the bug is not due to that common cause.
After some tries, i finally find a fix : declaring all the dma buffer volatile. I had to change all the API to add volatile on all functions which take that buffer address as a parameter.
I still don't understand why i had to declare this buffer volatile, since it is writen to by the CPU, *then* read by the DMA controler, there is never concurrent access.
If one has advice or explanation, i need to understand !
Thanks
Alexandre
My question is not chibios specific.
I have received a bug report on open source software that i wrote, on a dshot driver which basically fill a buffer which is transmitted (DMA) to a timer in pwm mode to make a pulse coded numeric signal respecting the dshot protocol. The bug report is : 7% of the frames are not correct.
The processor used is a F7, because of cache coherency problem, i took care of putting the global variable buffer in ram3, a ram section which is uncached, so the bug is not due to that common cause.
After some tries, i finally find a fix : declaring all the dma buffer volatile. I had to change all the API to add volatile on all functions which take that buffer address as a parameter.
I still don't understand why i had to declare this buffer volatile, since it is writen to by the CPU, *then* read by the DMA controler, there is never concurrent access.
If one has advice or explanation, i need to understand !
Thanks
Alexandre