strange coherency problem with dma buffer

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alex31
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strange coherency problem with dma buffer

Postby alex31 » Wed Jul 08, 2020 9:20 pm

Hello,

My question is not chibios specific.

I have received a bug report on open source software that i wrote, on a dshot driver which basically fill a buffer which is transmitted (DMA) to a timer in pwm mode to make a pulse coded numeric signal respecting the dshot protocol. The bug report is : 7% of the frames are not correct.

The processor used is a F7, because of cache coherency problem, i took care of putting the global variable buffer in ram3, a ram section which is uncached, so the bug is not due to that common cause.

After some tries, i finally find a fix : declaring all the dma buffer volatile. I had to change all the API to add volatile on all functions which take that buffer address as a parameter.

I still don't understand why i had to declare this buffer volatile, since it is writen to by the CPU, *then* read by the DMA controler, there is never concurrent access.

If one has advice or explanation, i need to understand !

Thanks
Alexandre

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Giovanni
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Re: strange coherency problem with dma buffer

Postby Giovanni » Thu Jul 09, 2020 8:36 am

It depends on the code that access the DMA buffer, adding volatile enforces the compiler to not attempt optimizations on buffer accesses.

You need to compare the asm code with and without volatile.

Giovanni

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Re: strange coherency problem with dma buffer

Postby alex31 » Fri Jul 10, 2020 2:21 pm

Finally, volatile fixing the problem was sot sufficient, real problem belongs to DMA bandwidth, and seems to be fixed playing with DMA priority.

ADC dma/irq priority == PWM dma/irq priority, no volatile : 7% of malformed dshot frame
ADC dma/irq priority < PWM dma/irq priority, dma buffer not volatile : 0.1 % of malformed dshot frame
ADC dma/irq priority < PWM dma/irq priority, dma buffer volatile : 0 % of malformed dshot frame

hope that this DMA priority change resolving the problem is not itself a side affect of a root cause that has not yet been discovered ...

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Re: strange coherency problem with dma buffer

Postby Giovanni » Fri Jul 10, 2020 2:51 pm

If you have multiple DMAs try splitting buffers in different SRAMs, that should mitigate bandwidth issues (try to keep each DMA master on a specific SRAM slave).

Giovanni


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