The fig.13 of the L6474 datasheet shows it clocks out the data on the rising edge.
Try and see.
ChibiOS public support forum for all topics not covered by a specific support forum.
You are right, I interpreted wrongly the figure 224 in my reference manual.
But I have another related question. Can I configure the SPI driver so that I can transmit data on the rising edge, but receive data on the falling edge?
This is how SPI always works in modes 1 and 2. (CPOL=0 CPHA=1; and CPOL=1 CPHA=0.) Don't think of transmit and receive, since those are byte-oriented. In fact you have to go below the "bit" level to separate it into the "drive output" and "sample input" steps. Remember that in SPI, both master and slave will drive their respective outputs on one clock edge, and then on the other clock edge they will both sample the signal driven by the other.
At CPOL=0 the base value of the clock is zero:
For CPHA=0, data are captured on the clock's rising edge (low→high transition) and data is propagated on a falling edge (high→low clock transition).
For CPHA=1, data are captured on the clock's falling edge and data is propagated on a rising edge.
At CPOL=1 the base value of the clock is one (inversion of CPOL=0):
For CPHA=0, data are captured on clock's falling edge and data is propagated on a rising edge.
For CPHA=1, data are captured on clock's rising edge and data is propagated on a falling edge.
That is, CPHA=0 means sample on the leading (first) clock edge, while CPHA=1 means sample on the trailing (second) clock edge, regardless of whether that clock edge is rising or falling. Note that with CPHA=0, the data must be stable for a half cycle before the first clock cycle.
(Source: Wikipedia:SPI Modes)
Who is online
Users browsing this forum: No registered users and 3 guests