SPI send problems

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diurpaneus
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Joined: Thu Sep 15, 2011 3:37 pm

SPI send problems

Postby diurpaneus » Thu Sep 15, 2011 4:20 pm

Hi,
I'm trying to use the SPI driver to test the communication. My chip is a STM32F100RBT6B. The problem seems to be that everything I send is different from what I insert in the buffer.
For example I try to send: 0xFA 0xD1 0xB0 0xBE ; but this is what is actually sent: F5 A3 61 7D. Here is the output from the logic analyzer: Image

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Here is the code I use:

Code: Select all

#define NSS          13       //PC13
#define   SPI_CHANNEL      SPID1   //Channel 1
static SPIConfig jn5148_spi_config_tx = {NULL, IOPORT3, NSS, SPI_CR1_BR_2 | SPI_CR1_BR_1|SPI_CR1_CPOL}; //used for transmitting and testing
static uint8_t status_padding2[4] = {0xFA,0xD1,0xB0,0xBE};

void testIP(void)
{
   palSetPadMode(IOPORT3, NSS,  PAL_MODE_OUTPUT_PUSHPULL);
   while( TRUE )
   {
      spiStart(&SPI_CHANNEL, &jn5148_spi_config_tx);
      spiSelect(&SPI_CHANNEL);
      spiSend(&SPI_CHANNEL,4, status_padding2);
      spiUnselect(&SPI_CHANNEL);
      spiStop(&SPI_CHANNEL);
               chThdSleepMilliseconds(2000);
   }

}
/*
 * Application entry point.
 */
int main(void) {

  /*
   * System initializations.
   * - HAL initialization, this also initializes the configured device drivers
   *   and performs the board-specific initializations.
   * - Kernel initialization, the main() function becomes a thread and the
   *   RTOS is active.
   */
  halInit();
  chSysInit();
  testIP();
}

I use ChibiOS 2.2.6.

Can somebody explain why this is happening?

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Giovanni
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Re: SPI send problems

Postby Giovanni » Thu Sep 15, 2011 5:42 pm

Hi,

The output is correct, you programmed the SPI using CPOL=1 and CHPA=0, according to Figure 224 of the STM32F100 RM this means that SPI is sampling the data on the descending front of the clock line. Reading the output of you program you can see:

1111101011010001.... -> FA D1.....

Probably your instrument is sampling the data on the rising clock edge, this would explain the difference.

Giovanni

diurpaneus
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Joined: Thu Sep 15, 2011 3:37 pm

Re: SPI send problems

Postby diurpaneus » Thu Sep 15, 2011 6:06 pm

Hi,
You are right, I interpreted wrongly the figure 224 in my reference manual.
Thanks.
But I have another related question. Can I configure the SPI driver so that I can transmit data on the rising edge, but receive data on the falling edge?

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Re: SPI send problems

Postby Giovanni » Thu Sep 15, 2011 6:23 pm

Hi,

It is not possible, in STM32 the SPI settings are shared between receiver and transmitter, you may use an external inverter on the clock line.

Giovanni

chibby
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Re: SPI send problems

Postby chibby » Tue Mar 31, 2015 4:58 am

Ah, this is just the sort of thing I came here to look for.

I'm using an ST produced board which is essentially a breakout board for their ( SPI configurable ) L6474 chip with Arduino format pinout.

http://www.st.com/web/en/catalog/tools/PF260715
http://www.farnell.com/datasheets/1698002.pdf

Now the spec sheet for the slave chip says that it does exactly this : rising for input, falling for output
This is specifically designed to work with their Nucleo range of demonstration boards. STM32 F3,F4

http://www.st.com/st-web-ui/static/acti ... 105918.pdf

Now these plug directly into each other, so no hardware inverter needed. (In fact it would be a major PITA.)
It is not possible, in STM32 the SPI settings are shared between receiver and transmitter, you may use an external inverter on the clock line.


Was that meaning that Chibios driver (rather than the hardware) uses shared settings? If so, would this be easy to change in the driver, or is likely to mess a lot of things up and need some serious debugging?

TIA.

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Re: SPI send problems

Postby Giovanni » Tue Mar 31, 2015 7:39 am

No, I meant that receive and transmitter use the same clock line and thus use the same settings for the clock, if you need two clock lines with inverted polarity then an inverter is required.

Giovanni

chibby
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Re: SPI send problems

Postby chibby » Tue Mar 31, 2015 9:45 am

Thanks Giovanni, but I still don't follow this.

diurpaneus
Can I configure the SPI driver so that I can transmit data on the rising edge, but receive data on the falling edge?


You replied that this was not possible. Maybe you misunderstood what he was asking or I'm misunderstanding your reply.

Since this is all about the STM32 family I'm assuming he was asking about a similar situation to that which I face with the L6474. It clocks incoming data on MOSI with rising edge and outputs data on MISO clocked on falling edge, but it's the same clock signal, provided by master on CK.

The boards I linked to are designed to stack onto each other and onto the Nucleo with the processor,so clearly they are intended to work together without inverting the clock.

Is there a problem in this situation with the current Chibios driver only having one shared configuration and hence one trigger edge setting for both directions.

I asked:
"Was that meaning that Chibios driver (rather than the hardware) uses shared settings? "
and you replied
"No, I meant that receive and transmitter use the same clock line and thus use the same settings for the clock,".


Yes, it is usual that there is a common clock line and that is the case here. Except that different edge detection is used in receive and transmit directions. I'm guessing by the confusion here that is maybe something that was not anticipated in Chibios driver.

If I am simply misunderstanding your reply could you indicate how the driver can be configured to deal with this situation, if not could you please comment on how difficult it would be modify the driver to support this situation.

Thanks.

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Re: SPI send problems

Postby Giovanni » Tue Mar 31, 2015 9:53 am

The real question is, does the STM32 SPI HW support that scenario? if so then the driver could support that.

Giovanni

chibby
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Re: SPI send problems

Postby chibby » Tue Mar 31, 2015 10:28 am

http://www.farnell.com/datasheets/1698002.pdf
8 Serial interface

All commands and data bytes are shifted into the device through the SDI input, most
significant bit first. The SDI is sampled on the rising edges of the CK.

All output data bytes are shifted out of the device through the SDO output, most significant
bit first. The SDO is latched on the falling edges of the CK. When a return value from the
device is not available, an all zero byte is sent.


A timing diagram follows that text.

Maybe I'm misreading the L6474 spec sheet but it seems that SDO should be read after it is latched.

From STM32F407xx reference:
2.2.24
Serial peripheral interface (SPI)
The STM32F40x feature up to three SPIs in slave and master modes in full-duplex and
simplex communication modes. SPI1 can communicate at up to 37.5 Mbits/s, SPI2 and
SPI3 can communicate at up to 21 Mbit/s. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the
DMA controller.
The SPI interface can be configured to operate in TI mode for communications in master
mode and slave mode.


Figure 33 shows a similar timing diagram to the one in L6474 data sheet.

EDIT.

OK, I think I get it. The output is latched on the falling edge and is thus stable by the time it is read by master on the following rising edge.

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Re: SPI send problems

Postby Giovanni » Tue Mar 31, 2015 11:03 am

then it is not matter of driver, this is how the STM32 SPI works. Transmitter and receiver use the same configuration.

Giovanni


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