variable mapping for STM32F769

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neums
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variable mapping for STM32F769

Postby neums » Thu Oct 04, 2018 9:48 am

Hi,
i am using the STM32F769. The initialized variables are linked to ram0 (alias DATA_RAM) and not initialized variables are linked to ram3 (alias BSS_RAM) which are different as the mapping is as follows:

Code: Select all

    ram0    : org = 0x20020000, len = 384k      /* SRAM1 + SRAM2 */
    ram1    : org = 0x20020000, len = 368k      /* SRAM1 */
    ram2    : org = 0x2007C000, len = 16k       /* SRAM2 */
    ram3    : org = 0x20000000, len = 128k      /* DTCM-RAM */

What is the technical reason for this?

Thank you.

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Giovanni
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Re: variable mapping for STM32F769

Postby Giovanni » Thu Oct 04, 2018 3:53 pm

Hi,

Cortex-M7 does not support HW cache coherency.

DTCM is not cached, this is done to make cache handling not required when buffers are placed in BSS (most common case). You may put BSS in a different RAM but then you need to take care of cache coherence manually.

Giovanni


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