Re: MIPS32 port
Posted: Wed Jul 10, 2013 6:42 pm
hi dmytro,
the first fix in SPI was definitely a typo - it caused wrong offset for brg register so brg was always set to 0.
The second one (cnt-1) - I am not really sure. Here is the story:
1. first I tried to make it work with SPI EEPROM (microchip 25AA02)
- when brg was set to 0, it worked but returned wrong data because clock speed was too fast for the EEPROM.
- after I fixed the clock, it started to hang with active RX channel. I found that SPI transmits one byte less than requested so I commented out "-1".
- the EEPROM started to work OK on 1MHz clock.
Btw, it seems to me that the first transmit is forced only when there is no triggering event:
dma_lld.c, line 244:
if (!cfg->evt)
dchx->econ.set = 1 << DMA_CHAN_ECON_CFORCE;
however the SPI driver always enables events for both tx and rx dma channels:
spi_lld.c, line 350:
dmaChannelCfg ccfg = {
.prio = DMA_CHANNEL_PRIO_LOWEST,
.fifownd = 1,
.evt = TRUE,
.eirq = cfg->rx_irq,
};
2. the second chip I tried was MRF24J40 which is capable of doing 10MHz. It did not work with DMA at all. The DMA always hung with some weird negative values in counter registers. Probably we must use SPI FIFO or something. Simple enabling the FIFO did not help though. I haven't dug any deeper.
My current goal is porting my MRF driver so I have temporarily given up on DMA and use polling.
Hopefully someone sometimes will have opportunity to return to this area.
the first fix in SPI was definitely a typo - it caused wrong offset for brg register so brg was always set to 0.
The second one (cnt-1) - I am not really sure. Here is the story:
1. first I tried to make it work with SPI EEPROM (microchip 25AA02)
- when brg was set to 0, it worked but returned wrong data because clock speed was too fast for the EEPROM.
- after I fixed the clock, it started to hang with active RX channel. I found that SPI transmits one byte less than requested so I commented out "-1".
- the EEPROM started to work OK on 1MHz clock.
Btw, it seems to me that the first transmit is forced only when there is no triggering event:
dma_lld.c, line 244:
if (!cfg->evt)
dchx->econ.set = 1 << DMA_CHAN_ECON_CFORCE;
however the SPI driver always enables events for both tx and rx dma channels:
spi_lld.c, line 350:
dmaChannelCfg ccfg = {
.prio = DMA_CHANNEL_PRIO_LOWEST,
.fifownd = 1,
.evt = TRUE,
.eirq = cfg->rx_irq,
};
2. the second chip I tried was MRF24J40 which is capable of doing 10MHz. It did not work with DMA at all. The DMA always hung with some weird negative values in counter registers. Probably we must use SPI FIFO or something. Simple enabling the FIFO did not help though. I haven't dug any deeper.
My current goal is porting my MRF driver so I have temporarily given up on DMA and use polling.
Hopefully someone sometimes will have opportunity to return to this area.