MIPS32 port

ChibiOS public support forum for topics related to the micro-controllers based on MIPS32 cores.

Moderator: Dmytro

Dmytro
Posts: 98
Joined: Sun Oct 07, 2012 11:49 am

Re: MIPS32 port

Postby Dmytro » Mon Feb 18, 2013 5:15 pm

For retrobsd it's fine to have such partitioning, but for chibios, which is completely executed in kernel mode, it does not make sense =/.

pito
Posts: 199
Joined: Sun Nov 06, 2011 3:54 pm

Re: MIPS32 port

Postby pito » Mon Feb 18, 2013 5:23 pm

And what do you need?

Dmytro
Posts: 98
Joined: Sun Oct 07, 2012 11:49 am

Re: MIPS32 port

Postby Dmytro » Mon Feb 18, 2013 5:29 pm

I want to put some functions into RAM(like vectors, ISRs, and maybe some "user" functions).

pito
Posts: 199
Joined: Sun Nov 06, 2011 3:54 pm

Re: MIPS32 port

Postby pito » Mon Feb 18, 2013 8:10 pm

afaik you can allocate the whole ram for kernel..

Dmytro
Posts: 98
Joined: Sun Oct 07, 2012 11:49 am

Re: MIPS32 port

Postby Dmytro » Mon Feb 18, 2013 8:44 pm

pito wrote:afaik you can allocate the whole ram for kernel..
According to the spec by default all RAM is reserved for "kernel DATA". With manipulation of bus matrix configuration you can reserve some space for "kernel TEXT", but there are some limitation. The granularity of the segment is 2K and since register width is 16 bits you can allocate only up to 0xF800 bytes per segment. If I don't use user space there's some waste in case of 128KiB SRAM. And in fact I'm not sure that I really need so much program space.

pito
Posts: 199
Joined: Sun Nov 06, 2011 3:54 pm

Re: MIPS32 port

Postby pito » Mon Feb 18, 2013 9:23 pm

Serge from retrobsd is the MIPS guy, he may provide you with an advice if needed.. I've sent a message to him..

Dmytro
Posts: 98
Joined: Sun Oct 07, 2012 11:49 am

Re: MIPS32 port

Postby Dmytro » Mon Feb 18, 2013 11:16 pm

Thanks Pito. But this is more PIC32 thing than MIPS-specific.
Anyway I did a small benchmark where all ISR are in SRAM and in fact this gives slight win only in timers tests. In other tests the results are significantly lower. I suppose that this is due to -mlong-calls.
I'm not a big expert of MIPS cores but seems like m4k has very simple branch predictor and it can't prefetch in advance if jump to register instruction is used(JR, JLR).
So this "execute from RAM" doesn't make any sense for me unless you put everything into SRAM.

pito
Posts: 199
Joined: Sun Nov 06, 2011 3:54 pm

Re: MIPS32 port

Postby pito » Tue Feb 19, 2013 1:41 am

Dmytro wrote:but seems like m4k has very simple branch predictor and it can't prefetch in advance if jump to register instruction is used(JR, JLR).

..once upon a time there was a discusion at retrosite on missed delay slots when talking J, JR; enabled/disabled reorder mode, etc..

rocketdawg
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Location: Idaho

Re: MIPS32 port

Postby rocketdawg » Fri Mar 15, 2013 5:35 pm

due to the harvard arch and the flash caching, it often will be slower to execute out of RAM with a PIC32.
the bus has to switch between reading code and read/write memory.
It gets even worse with a real fast peripheral DMA since almost half of the RAM bandwidth can be allocated to DMA.
Best to execute out of flash since the two buses can be fetching simultaneously.

Dmytro
Posts: 98
Joined: Sun Oct 07, 2012 11:49 am

Re: MIPS32 port

Postby Dmytro » Fri Mar 15, 2013 8:42 pm

rocketdawg wrote:due to the harvard arch and the flash caching, it often will be slower to execute out of RAM with a PIC32.
the bus has to switch between reading code and read/write memory.
It gets even worse with a real fast peripheral DMA since almost half of the RAM bandwidth can be allocated to DMA.
Best to execute out of flash since the two buses can be fetching simultaneously.

Yes, this makes sense!


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