STMH7 SPIv3 - MISO in slave mode
Posted: Sun Aug 09, 2020 8:42 pm
Hello ChibiOS fans
I am using SPIv3 driver on STM32H7 with the usual tweak in hal_spi_lld.c to allow STM to function as in SLAVE role. Generally there is no issue with communication to the MASTER (as both parties are configured for the same number of bytes in the SPI transaction), however in terms of SPI signaling it looks a little incorrect.
The image below shows STM driving MISO (yellow) low and then immediately released after the last byte is clocked. (DMA is used for the SPI transactions.)
The SPI MASTER continues to assert slave select (NSS, blue) low for a long while after the last CLK (pink). I think would be better if STM drive the MISO line until NSS is de-asserted...after all, it is being addressed by the MASTER during this time.
Just wondering if other people observe the same MISO behavior with their SPI SLAVE implementations and thoughts on resolution.
Thank you!
I am using SPIv3 driver on STM32H7 with the usual tweak in hal_spi_lld.c to allow STM to function as in SLAVE role. Generally there is no issue with communication to the MASTER (as both parties are configured for the same number of bytes in the SPI transaction), however in terms of SPI signaling it looks a little incorrect.
The image below shows STM driving MISO (yellow) low and then immediately released after the last byte is clocked. (DMA is used for the SPI transactions.)
The SPI MASTER continues to assert slave select (NSS, blue) low for a long while after the last CLK (pink). I think would be better if STM drive the MISO line until NSS is de-asserted...after all, it is being addressed by the MASTER during this time.
Just wondering if other people observe the same MISO behavior with their SPI SLAVE implementations and thoughts on resolution.
Thank you!