Cortex-M7: DTCM-RAM Section In Linker File

ChibiOS public support forum for topics related to the STMicroelectronics STM32 family of micro-controllers.

Moderators: barthess, RoccoMarco

Posts: 2
Joined: Fri May 29, 2015 11:17 pm

Cortex-M7: DTCM-RAM Section In Linker File

Postby egarcia » Mon Jun 15, 2020 4:43 am


In the STM32F743 example in v19.1.3 of ChibiOS, vectors.S, the first address placed in the .vectors section is __main_stack_end__, followed by Reset_Handler. Why is that?

Looking at the NVIC table in the reference manual, it has the first vector with an address offset of 0x00000000 labeled as "RESERVED", followed by the Reset vector. I understand that the Main stack is responsible for handling interrupts and exceptions, but the only thing I can find related to this is in the programming manual for Cortex-M7 where it states:
On reset, the processor loads the MSP with the value from address 0x00000000.
However address 0x00000000 is the starting address in the ITCM-RAM section. It doesn't look like the ITCM-RAM section is being utilized in the demo project though.

Thank you.

User avatar
Site Admin
Posts: 13085
Joined: Wed May 27, 2009 8:48 am
Location: Salerno, Italy
Has thanked: 759 times
Been thanked: 637 times

Re: Cortex-M7: DTCM-RAM Section In Linker File

Postby Giovanni » Mon Jun 15, 2020 7:02 am


The MSP value is fetched from the first element in the vectors table, probably the core is tricked into fetching from another location or the flash is placed at address zero during reset. The answer is somewhere in ST documents.


Return to “STM32 Support”

Who is online

Users browsing this forum: No registered users and 2 guests