In a non-ChibiOS project a while back, we wasted a lot of time with the STM SPI hardware : if you change clock mode with the clock in the wrong state, or accidentally create active clock edges during port initialisation, you end up clocking the SPI interface, and it stays one bit out of step with your expectations forever.
We ended up having to implement a master-slave 4 phase handshake between two STM32L151 micros where one was an SPI master and the other a SPI slave. The 4 phase handshake defined a point in time where both CPUs had set up all their GPIOs and then soft-reset their SPI controllers with all SPI signals in inactive states.
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