Flash wait state on STM32F103

ChibiOS public support forum for topics related to the STMicroelectronics STM32 family of micro-controllers.

Moderators: RoccoMarco, barthess

greb
Posts: 10
Joined: Tue Apr 05, 2016 12:50 pm
Has thanked: 2 times
Been thanked: 3 times

Flash wait state on STM32F103

Postby greb » Thu Nov 02, 2017 5:35 pm

Hi,

I'm currently debugging a strange instruction fetch problem that occurs on some F103 chips. I'm running the SYSCLK at 48 MHz. According to reference manual (chapter 3.3.3) I should use a wait state of 0x1, but instead FLASH->ACR has a wait state of 0x0. After some digging around in the HAL-Layer, I found the following code in hal_lld_f103.h:

/**
* @brief Flash settings.
*/
#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
#define STM32_FLASHBITS 0x00000010
#elif STM32_HCLK <= 48000000
#define STM32_FLASHBITS 0x00000011
#else
#define STM32_FLASHBITS 0x00000012
#endif


So, it seems the code uses the the AHB clock instead of the system clock to determine the flash wait state. Since I'm running HCLK at half the speed of SYSCLK (STM32_HPRE_DIV2) this produces the wrong SMT32_FLASHBITS configuration.

Is this a bug, or is this intended behavior?

Thanks,
greb

User avatar
Giovanni
Site Admin
Posts: 14444
Joined: Wed May 27, 2009 8:48 am
Location: Salerno, Italy
Has thanked: 1074 times
Been thanked: 921 times
Contact:

Re: Flash wait state on STM32F103

Postby Giovanni » Thu Nov 02, 2017 6:49 pm

Hi,

Looking at the clock tree on page 92 in RM0008 it is HCLK that drives the CPU and memory, I believe it is correct.

Giovanni


Return to “STM32 Support”

Who is online

Users browsing this forum: No registered users and 20 guests