Where to start STM32H7 support
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Re: Where to start STM32H7 support
I have tried with either STM32 HAL or FreeRTOS (or both? I don't remember exactly but can check and publish an example) and it was working while connected with loose wires. The card detected, writing and reading OK. Maybe there would be problems with the max. speed, but I haven't been adjusting any parameters and all was fine.
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Re: Where to start STM32H7 support
Note also that you can connect most of the pins directly to Nucleo's connectors, thus reducing the number of wires. Bend the pins on the card shield and connect only the wires where using another pin can't be avoided.
Re: Where to start STM32H7 support
Hi,
I hava question contected to the topic. I go through older post but I'm not sure, as for now, only Serial Driver module was tested for H7 or maybe You have some UART drivers examples? I tried to start UART drivers( chaneges in mcuconf.h and halconf.h from Blink exmaple for H7 Nuccleo) but I get many errors in hall_uart_lld.h (unkown definitions for example "UART7 DMA streams not defined") .
Best regards
Damian
I hava question contected to the topic. I go through older post but I'm not sure, as for now, only Serial Driver module was tested for H7 or maybe You have some UART drivers examples? I tried to start UART drivers( chaneges in mcuconf.h and halconf.h from Blink exmaple for H7 Nuccleo) but I get many errors in hall_uart_lld.h (unkown definitions for example "UART7 DMA streams not defined") .
Best regards
Damian
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Re: Where to start STM32H7 support
Hi,
UART is untested on H7, I need to review it. Could you post a note in "bug reports" about this? it is where I look for "things to do".
Giovanni
UART is untested on H7, I need to review it. Could you post a note in "bug reports" about this? it is where I look for "things to do".
Giovanni
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H743 hang in spiExchange()
I'm bringing up a H743 based board with ArduPilot. I got things building OK, but found that spiExchange() would never return. So I tried the testhal/STM32/multi/SPI test on a Nucleo-H743 board, and got the same issue. The circular buffer test on SPID1 hangs.
Can someone else confirm if that test is working for them? I notice SPI was listed as working by Giovannni back in Jan 2018, so I'm wondering if this is a regression or if it is something in my build environment (I'm using gcc 6.3.1).
The USB_CDC test is working fine on the same Nucleo board.
I also attach 3 patches for build errors I ran across while doing the port
Cheers, Tridge
Can someone else confirm if that test is working for them? I notice SPI was listed as working by Giovannni back in Jan 2018, so I'm wondering if this is a regression or if it is something in my build environment (I'm using gcc 6.3.1).
The USB_CDC test is working fine on the same Nucleo board.
I also attach 3 patches for build errors I ran across while doing the port
Cheers, Tridge
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- STM32H7-patches.zip
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Re: Where to start STM32H7 support
does anyone have a download of STM32CubeH7 they can share? The download on the ST site is corrupt.
I'm trying to work out the clock settings to get both the 48MHz OTG clock and an ADC clock in the required range for a H743. I can separately setup either ADC or OTG (and both work), but haven't yet worked out a clock tree that gives me both. I was thinking of trying STM32CubeH7 to see what it generates.
Cheers, Tridge
I'm trying to work out the clock settings to get both the 48MHz OTG clock and an ADC clock in the required range for a H743. I can separately setup either ADC or OTG (and both work), but haven't yet worked out a clock tree that gives me both. I was thinking of trying STM32CubeH7 to see what it generates.
Cheers, Tridge
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Re: Where to start STM32H7 support
tridge wrote:does anyone have a download of STM32CubeH7 they can share?
belay that ... I just realized ST offers downloads of old versions, and those aren't corrupt
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fix for PLL DIVP ranges for H7
I've got a working clock tree now (thanks to the CubeMX clock resolver). It ended up with a DIVP values for PLL2 of 1. That is marked as an error in the hal_lld.h, but as far as I can see from the ref manual, the lower limit of 2 only applies to PLL1.
I attach a patch to fix the limits for PLL2 and PLL3
I attach a patch to fix the limits for PLL2 and PLL3
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