I modified the STM32F0 discovery board and demo to the 030F4 part, so there may be some residual differences. They have the same max freq though, so the clock speed should be ok. Also with 16k of flash and 4k of ram maybe I should be trying the NIL rather than RT core.
mcuconf.h (just the top):
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#define STM32F0xx_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_HSI_ENABLED TRUE
#define STM32_HSI14_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED FALSE
#define STM32_LSE_ENABLED FALSE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSI_DIV2
#define STM32_PREDIV_VALUE 1
#define STM32_PLLMUL_VALUE 12
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE STM32_PPRE_DIV1
#define STM32_ADCSW STM32_ADCSW_HSI14
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_ADCSW STM32_ADCSW_HSI14
#define STM32_CECSW STM32_CECSW_HSI
#define STM32_I2C1SW STM32_I2C1SW_HSI
#define STM32_USART1SW STM32_USART1SW_PCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI
For the board.h I just removed the extra ports that the 030F4 chip doesn't have:
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/*
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* Setup for ST STM32F030F4 board.
*/
/*
* Board identifier.
*/
#define BOARD_ST_STM32F030F4
#define BOARD_NAME "ST STM32F030F4"
/*
* Board oscillators-related settings.
* NOTE: LSE not fitted.
* NOTE: HSE not fitted.
*/
#if !defined(STM32_LSECLK)
#define STM32_LSECLK 0U
#endif
#define STM32_LSEDRV (3U << 3U)
#if !defined(STM32_HSECLK)
#define STM32_HSECLK 0U
#endif
#define STM32_HSE_BYPASS
/*
* MCU type as defined in the ST header.
*/
#define STM32F030x4
/*
* IO pins assignments.
*/
#define GPIOA_BUTTON 0U
#define GPIOA_PIN1 1U
#define GPIOA_PIN2 2U
#define GPIOA_PIN3 3U
#define GPIOA_PIN4 4U
#define GPIOA_PIN5 5U
#define GPIOA_PIN6 6U
#define GPIOA_PIN7 7U
#define GPIOA_PIN8 8U
#define GPIOA_PIN9 9U
#define GPIOA_PIN10 10U
#define GPIOA_PIN11 11U
#define GPIOA_PIN12 12U
#define GPIOA_SWDAT 13U
#define GPIOA_SWCLK 14U
#define GPIOA_PIN15 15U
/*
* I/O ports initial setup, this configuration is established soon after reset
* in the initialization code.
* Please refer to the STM32 Reference Manual for details.
*/
#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
#define PIN_ODR_LOW(n) (0U << (n))
#define PIN_ODR_HIGH(n) (1U << (n))
#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
#define PIN_OSPEED_2M(n) (0U << ((n) * 2U))
#define PIN_OSPEED_10M(n) (1U << ((n) * 2U))
#define PIN_OSPEED_40M(n) (3U << ((n) * 2U))
#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
/*
* GPIOA setup:
*
* PA0 - BUTTON (input floating).
* PA1 - PIN1 (input pullup).
* PA2 - PIN2 (input pullup).
* PA3 - PIN3 (input pullup).
* PA4 - PIN4 (input pullup).
* PA5 - PIN5 (input pullup).
* PA6 - PIN6 (input pullup).
* PA7 - PIN7 (input pullup).
* PA8 - PIN8 (input pullup).
* PA9 - PIN9 (input pullup).
* PA10 - PIN10 (input pullup).
* PA11 - PIN11 (input pullup).
* PA12 - PIN12 (input pullup).
* PA13 - SWDAT (alternate 0).
* PA14 - SWCLK (alternate 0).
* PA15 - PIN15 (input pullup).
*/
#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \
PIN_MODE_INPUT(GPIOA_PIN1) | \
PIN_MODE_INPUT(GPIOA_PIN2) | \
PIN_MODE_INPUT(GPIOA_PIN3) | \
PIN_MODE_INPUT(GPIOA_PIN4) | \
PIN_MODE_INPUT(GPIOA_PIN5) | \
PIN_MODE_INPUT(GPIOA_PIN6) | \
PIN_MODE_INPUT(GPIOA_PIN7) | \
PIN_MODE_INPUT(GPIOA_PIN8) | \
PIN_MODE_INPUT(GPIOA_PIN9) | \
PIN_MODE_INPUT(GPIOA_PIN10) | \
PIN_MODE_INPUT(GPIOA_PIN11) | \
PIN_MODE_INPUT(GPIOA_PIN12) | \
PIN_MODE_ALTERNATE(GPIOA_SWDAT) | \
PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
PIN_MODE_INPUT(GPIOA_PIN15))
#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \
PIN_OTYPE_PUSHPULL(GPIOA_SWDAT) | \
PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_2M(GPIOA_BUTTON) | \
PIN_OSPEED_2M(GPIOA_PIN1) | \
PIN_OSPEED_2M(GPIOA_PIN2) | \
PIN_OSPEED_2M(GPIOA_PIN3) | \
PIN_OSPEED_2M(GPIOA_PIN4) | \
PIN_OSPEED_2M(GPIOA_PIN5) | \
PIN_OSPEED_2M(GPIOA_PIN6) | \
PIN_OSPEED_2M(GPIOA_PIN7) | \
PIN_OSPEED_2M(GPIOA_PIN8) | \
PIN_OSPEED_2M(GPIOA_PIN9) | \
PIN_OSPEED_2M(GPIOA_PIN10) | \
PIN_OSPEED_2M(GPIOA_PIN11) | \
PIN_OSPEED_2M(GPIOA_PIN12) | \
PIN_OSPEED_40M(GPIOA_SWDAT) | \
PIN_OSPEED_40M(GPIOA_SWCLK) | \
PIN_OSPEED_40M(GPIOA_PIN15))
#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \
PIN_PUPDR_PULLUP(GPIOA_PIN1) | \
PIN_PUPDR_PULLUP(GPIOA_PIN2) | \
PIN_PUPDR_PULLUP(GPIOA_PIN3) | \
PIN_PUPDR_PULLUP(GPIOA_PIN4) | \
PIN_PUPDR_PULLUP(GPIOA_PIN5) | \
PIN_PUPDR_PULLUP(GPIOA_PIN6) | \
PIN_PUPDR_PULLUP(GPIOA_PIN7) | \
PIN_PUPDR_PULLUP(GPIOA_PIN8) | \
PIN_PUPDR_PULLUP(GPIOA_PIN9) | \
PIN_PUPDR_PULLUP(GPIOA_PIN10) | \
PIN_PUPDR_PULLUP(GPIOA_PIN11) | \
PIN_PUPDR_PULLUP(GPIOA_PIN12) | \
PIN_PUPDR_PULLUP(GPIOA_SWDAT) | \
PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \
PIN_PUPDR_PULLUP(GPIOA_PIN15))
#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \
PIN_ODR_HIGH(GPIOA_PIN1) | \
PIN_ODR_HIGH(GPIOA_PIN2) | \
PIN_ODR_HIGH(GPIOA_PIN3) | \
PIN_ODR_HIGH(GPIOA_PIN4) | \
PIN_ODR_HIGH(GPIOA_PIN5) | \
PIN_ODR_HIGH(GPIOA_PIN6) | \
PIN_ODR_HIGH(GPIOA_PIN7) | \
PIN_ODR_HIGH(GPIOA_PIN8) | \
PIN_ODR_HIGH(GPIOA_PIN9) | \
PIN_ODR_HIGH(GPIOA_PIN10) | \
PIN_ODR_HIGH(GPIOA_PIN11) | \
PIN_ODR_HIGH(GPIOA_PIN12) | \
PIN_ODR_HIGH(GPIOA_SWDAT) | \
PIN_ODR_HIGH(GPIOA_SWCLK) | \
PIN_ODR_HIGH(GPIOA_PIN15))
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0) | \
PIN_AFIO_AF(GPIOA_PIN1, 0) | \
PIN_AFIO_AF(GPIOA_PIN2, 0) | \
PIN_AFIO_AF(GPIOA_PIN3, 0) | \
PIN_AFIO_AF(GPIOA_PIN4, 0) | \
PIN_AFIO_AF(GPIOA_PIN5, 0) | \
PIN_AFIO_AF(GPIOA_PIN6, 0) | \
PIN_AFIO_AF(GPIOA_PIN7, 0))
#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \
PIN_AFIO_AF(GPIOA_PIN9, 0) | \
PIN_AFIO_AF(GPIOA_PIN10, 0) | \
PIN_AFIO_AF(GPIOA_PIN11, 0) | \
PIN_AFIO_AF(GPIOA_PIN12, 0) | \
PIN_AFIO_AF(GPIOA_SWDAT, 0) | \
PIN_AFIO_AF(GPIOA_SWCLK, 0) | \
PIN_AFIO_AF(GPIOA_PIN15, 0))
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
#endif
void boardInit(void);
#ifdef __cplusplus
}
#endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H_ */
Here's the trace:
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(gdb) bt
#0 _unhandled_exception () at ../../../os/common/ports/ARMCMx/compilers/GCC/vectors.c:77
#1 <signal handler called>
#2 0x55555554 in ?? ()
Backtrace stopped: previous frame identical to this frame (corrupt stack?)
looks like even though it compiled and flashed, there may still be some issues with the memory setup. I also had to disable LTO to get it to compile with the version of arm-none-eabi-gcc I'm using (5.1.0 arch linux)