ChibiOS Free Embedded RTOS

I'm currently integrating ChibiOS into another framework, and it is evident that I need separate configuration paths for where to find chconf.h, halconf.h, and mcuconf.h . It makes sense too from a Chibi product offering standpoint since the OS and HAL are separate modules. Currently the makefiles (...

Giovanni wrote:Hi,

It would be safe if done in a critical zone, so use chSysLock/Unlock.

Giovanni

Wouldn't one also need to preform a reschedule before exiting the critical zone?

Giovanni wrote:It is being moved at top level in new drivers, old drivers will be updated but it is not high priority.

Giovanni

Cool, so the new standard is to have the definition in the top level header file, with platform specific structure members included as macros defined in the lld driver?

The HAL driver object is defined in either in the top level hal_xxx.h file, or the hal_xxx_lld.h file depending on the driver. There should be one consistent pattern across all drivers.

Do you have an example for this? I am reluctant to support this kind of things because it would depend on the library (newlib) and how the library is compiled (reentrant or not). Giovanni Not sure if it should be part of standard ChibiOS distribution. Perhaps part of the optional syscalls, and have...

Hi, It is not something we control, the compiler maintainers have to decide this. Consider that supporting that "impure pointer" thing would slow down the system and a multithreaded lib is not necessarily useful for everybody and larger. Giovanni Going thru the exercise right now, it's no...

Thanks for the detailed reply!

Hi, It looks interesting, I cannot give it a try right now, too many things ongoing, I would appreciate some feedback about it. It would help to know how to try it. Giovanni It's pretty cool, we've been using it internally for a while now. So, it's battle tested code to some degree. CAN: Using sock...

It is not a runtime barrier, it is a logical barrier for the compiler. That " : memory" tells the compiler that the asm instruction can change memory (even if it is not true), the compiler can no more assume that "n" is unchanged across the asm statement. Giovanni Cool, you just...

Thanks for the example Giovanni. How does the compiler know it shouldn't cache n in a register after an msr instruction? I don't see any memory or data barrier instructions generated. This is the documentation of the MSR instruction I read: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc...