ChibiOS Free Embedded RTOS

Hi, Incorrect TX DMA channel assigned for UART5. -- Bob Index: stm32_registry.h =================================================================== --- stm32_registry.h (revision 13517) +++ stm32_registry.h (working copy) @@ -1541,7 +1541,7 @@ #define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1...

Hi,
USARTv1 currently assumes the DMA channel of a UART is the same for both RX and TX.
However, not all UARTs have the same DMA channel for RX and TX (e.g. F413 UART5).
The driver is updated to use separate DMA mode settings for RX and TX.
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Bob

Fixed as bug #1080

Fixed as bug #1079

Hi, Incorrect setting for F413 UART10 DMA streams. Patch of F4 stm32_registry.h follows. -- Bob Index: stm32_registry.h =================================================================== --- stm32_registry.h (revision 13489) +++ stm32_registry.h (working copy) @@ -1570,10 +1570,10 @@ #define STM32_...

Hi, On L4+ the IRQ vectors for I2C4 are reversed versus I2C1, 2 & 3. Also the bdma flag as not set correctly in the I2Cv3 driver. Patch below. -- Bob Index: os/hal/ports/STM32/LLD/I2Cv3/hal_i2c_lld.c =================================================================== --- os/hal/ports/STM32/LLD/I...

Hi, L4/L4+ allow PLLSAI1R or SYSCLK as ADC clock source supplying the "AHB" prescaler. In ADCv3 the test of the selected ADC clock frequency for L4/L4+ is done against STM32_HCLK. The check should be against STM32_ADCCLK. -- Bob Index: os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h ===========...

Hi,
88167 & 88656 fixed on 2019-10-25 on all active branches.
GCC active branch releases subsequent to the fix...
GCC 7.5 [2019-11-14]
GCC 8.4 [2020-03-04]
GCC 9.3 [2020-03-12]
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Bob

Alex,
The BRR assert is a minor pending fix to be applied.
viewtopic.php?f=35&t=5378
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Bob

Hi,
Still waiting for NUCLEO-G4xx stock to arrive in AU.
Current ETA April 6 so no go on USB test by me ATM.
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Bob