ChibiOS Free Embedded RTOS

Hi Giovanni, I think I found another issue with QSPIv2 Driver, so for receiving data instructions we are ending wait on Transfer Finish interrupt, but the MDMA transfers might not have pulled all the data from FIFO yet. I believe right path for Receive call to finish is in MDMA interrupt. For send I...

Yes, that's what I have been using. But I have been having issue with DMA caching. For some reason occasionally SCB_CleanInvalidateCache() seems to not work, I tried disabling Cache altogether, but somehow that also fails with stack corruption when AXI SRAM is set for Stack memory. I am probably goi...

Hi Giovanni, Please find the patches for the changes I added below. patches.zip Patch "0002-QSPIv2-set-FCR-to-clear-pending-flags-if-any.patch" is just out of paranoia, I didn't as such notice any issue except when using TC signal, which sometimes remained set when arriving at this line, I...

Yeah, that fixed the issue, the RAM was set to be cacheable, I just added SCB_CleanInvalidateDCache(); before wspiReceive return to quickly test this. But ofcourse the right way would be to disable the Cache on the region entirely. Additionally Transfer Complete signal to MDMA doesn't work for Recei...

Great! will be waiting for the sample code.

Hi Giovanni,
I will certainly do that. Any thoughts on tracking down the MDMA issue?

I have been trying to interface with MT25Q using QSPIv2. I have send command working perfectly including the MDMA, but I had to make changes to QSPIv2 driver. Firstly, I noticed a clear bug in the following lines of code: uint32_t ccr = STM32_MDMA_CCR_PL(STM32_WSPI_QUADSPI1_MDMA_PRIORITY) | STM32_MD...

Hi, I am trying to do a mutex lock inside the virtual timer callback set using chVTSet method. But I see that from the chSysUnlock i.e. called from while being inside the callback for mutex lock leads to debug error, Priority order violation. the value of ch.rlist.current is idle_thread context and ...