Hi,
I will create experimental driver for STR32WL to present idea,
with this example it will be easier to discuss approach. There is no need to change anything in HAL right now to implement PWR driver.
Search found 163 matches
- Sun Apr 25, 2021 8:11 pm
- Forum: Development and Feedback
- Topic: Power Driver for stm32l1
- Replies: 24
- Views: 12440
- Fri Apr 23, 2021 5:09 pm
- Forum: ChibiOS/HAL
- Topic: STM32WLxx port
- Replies: 61
- Views: 19093
Re: STM32WLxx port
Need some time to analyse what can be reused, WL has slightly different RCC.
Will return with new version based on L4 soon.
Will return with new version based on L4 soon.
- Fri Apr 23, 2021 8:42 am
- Forum: ChibiOS/HAL
- Topic: STM32WLxx port
- Replies: 61
- Views: 19093
Re: STM32WLxx port
Hi,
all changes committed to svn repository.
note:
initially hal_lld.c for stm32wl was based on hal_lld.c for stm32l4, and I've just noted that MSIPLL activation made twice in hal_lld.c: in stm32_clock_init and in hal_lld_backup_domain_init. Is it made intentionally?
all changes committed to svn repository.
note:
initially hal_lld.c for stm32wl was based on hal_lld.c for stm32l4, and I've just noted that MSIPLL activation made twice in hal_lld.c: in stm32_clock_init and in hal_lld_backup_domain_init. Is it made intentionally?
- Wed Apr 21, 2021 8:23 pm
- Forum: ChibiOS/HAL
- Topic: STM32WLxx port
- Replies: 61
- Views: 19093
Re: STM32WLxx port
Hi, new update is attached. RTC problem fixed and tested: RTC works, Alarms work. Change log: renamed: demos/STM32/RT-STM32WL55JC-NUCLEO/Makefile -> demos/STM32/RT-STM32WL55JC-NUCLEO64/Makefile renamed: demos/STM32/RT-STM32WL55JC-NUCLEO/cfg/chconf.h -> demos/STM32/RT-STM32WL55JC-NUCLEO64/cfg/chconf....
- Mon Apr 19, 2021 10:17 pm
- Forum: ChibiOS/HAL
- Topic: STM32WLxx port
- Replies: 61
- Views: 19093
Re: STM32WLxx port
RTC initialisation problem solved. RCC_APB1ENR1 RTCAPBEN was not enabled.
Not sure where is the best place to enable it. Is it ok to do it in hal_lld_backup_domain_init HAL_USE_RTC part?
Not sure where is the best place to enable it. Is it ok to do it in hal_lld_backup_domain_init HAL_USE_RTC part?
- Mon Apr 19, 2021 9:22 pm
- Forum: ChibiOS/HAL
- Topic: STM32WLxx port
- Replies: 61
- Views: 19093
Re: STM32WLxx port
The same problem with LSE as clock source for RTC.
RTC does not enter initialization mode.
RTC does not enter initialization mode.
- Mon Apr 19, 2021 7:51 pm
- Forum: ChibiOS/HAL
- Topic: STM32WLxx port
- Replies: 61
- Views: 19093
Re: STM32WLxx port
As I understand everything is ok: RCC->CSR LSION [0:0] 0b1 LSIRDY [1:1] 0b1 LSIPRE [4:4] 0b0 RCC->BDSR RTCSEL [9:8] 0b10 - LSI RTCEN [15:15] 0b1 mcuconf.h #define STM32_LSI_ENABLED TRUE #define STM32_LSIPRE STM32_LSIPRE_NODIV #define STM32_RTCSEL STM32_RTCSEL_LSI
- Mon Apr 19, 2021 7:23 pm
- Forum: ChibiOS/HAL
- Topic: STM32WLxx port
- Replies: 61
- Views: 19093
Re: STM32WLxx port
Strange situation with RTC init, RTC->ICSR INITF flag is constantly 0 after RTCD1.rtc->ICSR |= RTC_ICSR_INIT;
PWR->CR1 DBP is 1
Write protection is disabled.
Any idea what could be wrong?
PWR->CR1 DBP is 1
Write protection is disabled.
Any idea what could be wrong?
- Mon Apr 19, 2021 10:27 am
- Forum: ChibiOS/HAL
- Topic: STM32WLxx port
- Replies: 61
- Views: 19093
Re: STM32WLxx port
And what about TAMP? - STM32WLxx has additional flag TAMP_CR2 BKERASE: Backup registers erase - should Backup registers be erased on RTC initialisation? - STM32WLxx has additional register TAMP_CR3 - should it be initialised with specific value or default value ok (default - not erase backup on temp...
- Mon Apr 19, 2021 10:16 am
- Forum: ChibiOS/HAL
- Topic: STM32WLxx port
- Replies: 61
- Views: 19093
Re: STM32WLxx port
According this doc: https://www.st.com/resource/en/application_note/dm00226326-using-the-hardware-realtime-clock-rtc-and-the-tamper-management-unit-tamp-with-stm32-microcontrollers-stmicroelectronics.pdf STM32G0, G1, WL... have all RTC3 But yes, WL does not have ALRAWF/ALRBWF and according documenta...