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by FXCoder
Tue Nov 24, 2020 10:59 am
Forum: Development and Feedback
Topic: STM32WB55 support
Replies: 35
Views: 3732

Re: STM32WB55 support

Giovanni, Sounds good on the helper driver approach for IPCC and HSE How about proceeding as follows: 1. Add the latest WB55 work by Ilya to trunk. 2. Then WB standard peripheral work/fixes continue as required in trunk. 3. The iPCC and HSE helper drivers can be started (get implementation clues out...
by FXCoder
Tue Nov 24, 2020 12:44 am
Forum: Development and Feedback
Topic: STM32WB55 support
Replies: 35
Views: 3732

Re: STM32WB55 support

Hi,
Interesting progress and would be useful for upcoming projects I have.
Could IPCC & HSE become ChibiOS drivers since these are needed for STM32WL as well?
We'll get Giovanni's comments on that...
--
Bob
by FXCoder
Wed Nov 18, 2020 11:25 pm
Forum: ChibiOS/RT
Topic: ChibiOS OS Library Test Suite
Replies: 6
Views: 149

Re: ChibiOS OS Library Test Suite

Hi,
I just did a quick check on a L432 NUCLEO and found main memory decreased after each 'test oslib'.
Could it be that a factory object is not being released (left dangling with heap allocated)?
--
Bob
by FXCoder
Wed Nov 18, 2020 12:03 am
Forum: Development and Feedback
Topic: toward secure embedded systems
Replies: 4
Views: 169

Re: toward secure embedded systems

This thread brought a smile to my face... The synchronous mode described is very reminiscent of circa 1970 Single interrupt and multiple Priority Level OS. The system interrupt takes you to the top of the "application" priority level for normal tasks. As each Priority Level is "comple...
by FXCoder
Mon Nov 02, 2020 12:33 pm
Forum: STM32 Support
Topic: Half-Duplex burst mode DMAR
Replies: 10
Views: 356

Re: Half-Duplex burst mode DMAR

Hi Andy,
I think we've gone out of scope of the original question.
For existing hardware then you'll need to work within the constraints of that design.
If it were a new design then the story could be different.
--
Bob
by FXCoder
Fri Oct 30, 2020 12:07 am
Forum: STM32 Support
Topic: Half-Duplex burst mode DMAR
Replies: 10
Views: 356

Re: Half-Duplex burst mode DMAR

Hi Andy, If you want to capture high speed PWM (i.e. the ChibiOS ICU driver isn't fast enough) and get the timer counts for each pulse/valley using DMA then for a single channel you'd need to setup two DMA streams and timer configuration as follows: 1. A TIM CH trigger on the edge (trailing in this ...
by FXCoder
Sun Oct 25, 2020 10:48 am
Forum: STM32 Support
Topic: Half-Duplex burst mode DMAR
Replies: 10
Views: 356

Re: Half-Duplex burst mode DMAR

Hi,
Have you set the DMA transfer size through DMAR to halfword?
Which TIM registers are you writing to/reading from?
--
Bob
by FXCoder
Mon Aug 24, 2020 3:56 pm
Forum: General Support
Topic: STM32L4R5ZI-NUCLEO144: How to activate the I2C4 bus on mcuconf.h?
Replies: 11
Views: 375

Re: STM32L4R5ZI-NUCLEO144: How to activate the I2C4 bus on mcuconf.h?

OK. Understand now what you meant.
The I2C4 driver did have a bug but that was fixed a while back.

Bob

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