Search found 162 matches

by FXCoder
Mon Mar 11, 2019 2:14 pm
Forum: Bug Reports
Topic: Any reason for dropping functions from guarded pools? Topic is solved
Replies: 3
Views: 98

Re: Any reason for dropping functions from guarded pools? Topic is solved

Thanks.
I was using the get counter in an assert to check if all pool members were released prior to destroying the pool.
I’ll resurrect that assert now.
by FXCoder
Mon Mar 11, 2019 10:59 am
Forum: Bug Reports
Topic: I2Cv3 update to use new dmaStreamFree(...) instead of dmaStreamRelease(...) Topic is solved
Replies: 3
Views: 101

Re: I2Cv3 update to use new dmaStreamFree(...) instead of dmaStreamRelease(...) Topic is solved

Doing some more on the L4+ based version of Pecan project this week so we’ll keep you advised of any more findings.

Bob
by FXCoder
Mon Mar 11, 2019 6:35 am
Forum: Bug Reports
Topic: Any reason for dropping functions from guarded pools? Topic is solved
Replies: 3
Views: 98

Any reason for dropping functions from guarded pools? Topic is solved

Were these dropped for any reason from chmempools.h when os/lib became os/oslib? /** * @brief Gets the count of objects in a guarded memory pool. * @pre The guarded memory pool must be already been initialized. * * @param[in] gmp pointer to a @p guarded_memory_pool_t structure * * @iclass */ static ...
by FXCoder
Mon Mar 11, 2019 2:40 am
Forum: Bug Reports
Topic: I2Cv3 update to use new dmaStreamFree(...) instead of dmaStreamRelease(...) Topic is solved
Replies: 3
Views: 101

I2Cv3 update to use new dmaStreamFree(...) instead of dmaStreamRelease(...) Topic is solved

Index: hal_i2c_lld.c =================================================================== --- hal_i2c_lld.c (revision 12685) +++ hal_i2c_lld.c (working copy) @@ -981,8 +981,8 @@ #endif #if defined(STM32_I2C_BDMA_REQUIRED) { - bdmaStreamRelease(i2cp->rx.bdma); - bdmaStreamRelease(i2cp->tx.bdma); + bd...
by FXCoder
Mon Mar 11, 2019 2:28 am
Forum: Bug Reports
Topic: Handling differences in ST EXTI header for STM32L4XXP Topic is solved
Replies: 1
Views: 66

Handling differences in ST EXTI header for STM32L4XXP Topic is solved

In GPIOv3 the L4+ series as well as the L4 needs to have its EXTI register names defined.

Line 34 of hal_pal_lld.c to become...

Code: Select all

#if defined(STM32L4XX) || defined(STM32L4XXP)

--
Bob
by FXCoder
Tue Feb 19, 2019 11:32 am
Forum: STM32 Support
Topic: Where to start STM32H7 support
Replies: 146
Views: 10895

Re: Where to start STM32H7 support

The language in the RM is a little challenging to read WRT the FIFO packing in the SPI controller. I thought perhaps using DMA removes the requirement for setting TSIZE. However, the RM does say the following which seems to suggest that TSIZE must be set regardless of packing, etc. Data packing with...
by FXCoder
Tue Feb 19, 2019 1:41 am
Forum: STM32 Support
Topic: Where to start STM32H7 support
Replies: 146
Views: 10895

Re: Where to start STM32H7 support

Hi,
Could this be related to the setting of SPI CR2:TSIZE?
TSIZE is set to 0 in spi_lld_start but not set to the actual transfer size when exchange, send or receive are called.
If TSIZE is 0 then the SPI peripheral is set for an endless transaction which may cause an unexpected extra transfer?
--
Bob
by FXCoder
Sat Feb 02, 2019 2:24 pm
Forum: Development and Feedback
Topic: [INFO] Solution for shared IRQs on STM32
Replies: 7
Views: 479

Re: [INFO] Solution for shared IRQs on STM32

Hi,
No problem.
1. I thought I had followed the L4+ pattern which has only the shared timers in the system IRQ section of mcuconf.
So L4+ demo has also to be updated?

2. OK on missing guards.

3. OK. I missed the testhal.

Agreed updater will make things easier.

--
Bob
by FXCoder
Tue Jan 29, 2019 11:18 pm
Forum: STM32 Support
Topic: STM32F4 DMA Peripheral-to-Memory: Memory Corruption
Replies: 12
Views: 901

Re: STM32F4 DMA Peripheral-to-Memory: Memory Corruption

Hi, OK. Your DMA reference is good. My mistake. The full macro I was thinking of should have been... STM32_DMA_STREAM(STM32_DMA_STREAM_ID(2, 2)); Regarding a way to sync DMA start... One way would be to use a pal callback (e.g. on leading edge) from the word sync pulse on a GPIO line. That call back...
by FXCoder
Tue Jan 29, 2019 12:30 am
Forum: STM32 Support
Topic: STM32F4 DMA Peripheral-to-Memory: Memory Corruption
Replies: 12
Views: 901

Re: STM32F4 DMA Peripheral-to-Memory: Memory Corruption

Hi, Some thoughts... To use the timer purely as a DMA trigger there is no need to involve Slave Mode. You don't care about the timer value in such a use case. Just the trigger event. So just leave SMCR reset. Capture Input mode will produce a CC event at the edge transition(s) of the timer trigger i...

Go to advanced search